> -----Original Message----- > From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org] > Sent: Wednesday, July 10, 2013 5:23 PM > To: Wang Dongsheng-B40534 > Cc: Wood Scott-B07421; ga...@kernel.crashing.org; Zhao Chenhui-B35336; Li > Yang-R58472 > Subject: Re: [RFC 2/2] powerpc/cputable: add wait feature for CPU kernel > features > > On Wed, 2013-07-10 at 16:27 +0800, Dongsheng Wang wrote: > > From: Wang Dongsheng <dongsheng.w...@freescale.com> > > This is missing an explanation of what that feature bit means... > > possibly with a description of the corresponding HW feature. > > Ben. > Yes, the wait instructions is for cpu idle, It will be make cpu into low power mode, like DOZE & NAP. Each thread have this.
> > Signed-off-by: Wang Dongsheng <dongsheng.w...@freescale.com> > > > > diff --git a/arch/powerpc/include/asm/cputable.h > b/arch/powerpc/include/asm/cputable.h > > index 6f3887d..0a8d0cb 100644 > > --- a/arch/powerpc/include/asm/cputable.h > > +++ b/arch/powerpc/include/asm/cputable.h > > @@ -138,6 +138,7 @@ extern const char *powerpc_base_platform; > > #define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000) > > #define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000) > > #define CPU_FTR_EMB_HV ASM_CONST(0x40000000) > > +#define CPU_FTR_CAN_WAIT ASM_CONST(0x80000000) > > > > /* > > * Add the 64-bit processor unique features in the top half of the > word; > > @@ -250,9 +251,11 @@ extern const char *powerpc_base_platform; > > #ifndef CONFIG_BDI_SWITCH > > #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE > > #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP > > +#define CPU_FTR_MAYBE_CAN_WAIT CPU_FTR_CAN_WAIT > > #else > > #define CPU_FTR_MAYBE_CAN_DOZE 0 > > #define CPU_FTR_MAYBE_CAN_NAP 0 > > +#define CPU_FTR_MAYBE_CAN_WAIT 0 > > #endif > > > > #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ > > @@ -370,15 +373,17 @@ extern const char *powerpc_base_platform; > > CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) > > #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ > > CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ > > - CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) > > + CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | \ > > + CPU_FTR_MAYBE_CAN_WAIT) > > #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ > > CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ > > CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ > > - CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) > > + CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_MAYBE_CAN_WAIT) > > #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ > > CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ > > CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ > > - CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP) > > + CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | > \ > > + CPU_FTR_MAYBE_CAN_WAIT) > > #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | > CPU_FTR_NODSISRALIGN) > > > > /* 64-bit CPUs */ > > _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
