Shaohui -- Xie Shaohui-B21989 <b21...@freescale.com> writes:
> Thanks for the confirmation. You're very welcome. > So it seems the NOR write break the signal Integrity of SATA. > I don't have schematic and board right now, could you please measure > signals related to NOR write to see if anything abnormal? Is the board > use FPGA or CPLD to control signal? I'll have to pass these questions on to my hardware vendor; I'm not equipped to do this level of hardware debugging (neither hardware nor knowledge!). > If stop NOR write, could the SATA recover and work? Earlier in my development, I was seeing this error and it would recover: ata2: exception Emask 0x10 SAct 0x0 SErr 0x0 action 0xe frozen ata2: PHY RDY changed ata2: hard resetting link ata2: Signature Update detected @ 0 msecs ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 310) ata2.00: configured for UDMA/133 ata2: EH complete At the current time, however, it seems that it does not recover. I don't know whether this is due to the speed limiting code, or if it's because we are doing more disk accesses (when the actual product is up and running). I can re-do the tests with the speed limit disabled, but I won't be able to get to that for a few hours yet. You can read about the speed limit issues in this thread: http://article.gmane.org/gmane.linux.ports.ppc.embedded/50652 And my final patch (yes, a year later): http://article.gmane.org/gmane.linux.ports.ppc.embedded/58969 Please don't laugh too hard when you read it. :) Thanks again for your help. I'll try to get the results of testing w/o speed limit to you within a day or two. Best regards, Anthony Foiani _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
