On Mon, Apr 29, 2013 at 01:07:39AM +0530, Aneesh Kumar K.V wrote: > From: "Aneesh Kumar K.V" <aneesh.ku...@linux.vnet.ibm.com> > > Encode the actual page correctly in tlbie/tlbiel. This make sure we handle > multiple page size segment correctly.
As mentioned in previous comments, this commit message needs to give
much more detail about what precisely the existing implementation is
doing wrong.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com>
> ---
> arch/powerpc/mm/hash_native_64.c | 32 ++++++++++++++++++++++++++++++--
> 1 file changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/mm/hash_native_64.c
> b/arch/powerpc/mm/hash_native_64.c
> index bb920ee..6a2aead 100644
> --- a/arch/powerpc/mm/hash_native_64.c
> +++ b/arch/powerpc/mm/hash_native_64.c
> @@ -61,7 +61,10 @@ static inline void __tlbie(unsigned long vpn, int psize,
> int apsize, int ssize)
>
> switch (psize) {
> case MMU_PAGE_4K:
> + /* clear out bits after (52) [0....52.....63] */
> + va &= ~((1ul << (64 - 52)) - 1);
> va |= ssize << 8;
> + va |= mmu_psize_defs[apsize].sllp << 6;
> asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
> : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
> : "memory");
> @@ -69,9 +72,20 @@ static inline void __tlbie(unsigned long vpn, int psize,
> int apsize, int ssize)
> default:
> /* We need 14 to 14 + i bits of va */
> penc = mmu_psize_defs[psize].penc[apsize];
> - va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
> + va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
> va |= penc << 12;
> va |= ssize << 8;
> + /* Add AVAL part */
> + if (psize != apsize) {
> + /*
> + * MPSS, 64K base page size and 16MB parge page size
> + * We don't need all the bits, but rest of the bits
> + * must be ignored by the processor.
> + * vpn cover upto 65 bits of va. (0...65) and we need
> + * 58..64 bits of va.
I can't understand what this comment is saying. Why do we need to do
something different in the psize != apsize case?
> + */
> + va |= (vpn & 0xfe);
> + }
> va |= 1; /* L */
> asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
> : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
> @@ -96,16 +110,30 @@ static inline void __tlbiel(unsigned long vpn, int
> psize, int apsize, int ssize)
>
> switch (psize) {
> case MMU_PAGE_4K:
> + /* clear out bits after(52) [0....52.....63] */
> + va &= ~((1ul << (64 - 52)) - 1);
> va |= ssize << 8;
> + va |= mmu_psize_defs[apsize].sllp << 6;
> asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
> : : "r"(va) : "memory");
> break;
> default:
> /* We need 14 to 14 + i bits of va */
> penc = mmu_psize_defs[psize].penc[apsize];
> - va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
> + va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
> va |= penc << 12;
> va |= ssize << 8;
> + /* Add AVAL part */
> + if (psize != apsize) {
> + /*
> + * MPSS, 64K base page size and 16MB parge page size
> + * We don't need all the bits, but rest of the bits
> + * must be ignored by the processor.
> + * vpn cover upto 65 bits of va. (0...65) and we need
> + * 58..64 bits of va.
> + */
> + va |= (vpn & 0xfe);
> + }
> va |= 1; /* L */
> asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
> : : "r"(va) : "memory");
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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