IFC_FIR_OP_CMD0 issues command for execution without checking flash
readiness. It may cause problem if flash is not ready. Instead use
IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or
time-out, before issuing command.
NAND_CMD_READID command implemention does not fulfill above requirement. So
update its programming.
Signed-off-by: Prabhakar Kushwaha <prabha...@freescale.com>
Signed-off-by: Hemant Nautiyal <hemant.nauti...@freescale.com>
---
Based upon git://git.infradead.org/linux-mtd.git branch master
drivers/mtd/nand/fsl_ifc_nand.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 8f0dd13..7e5b17c 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -382,7 +382,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned
int command,
timing = IFC_FIR_OP_RBCD;
out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
(timing << IFC_NAND_FIR0_OP2_SHIFT));
out_be32(&ifc->ifc_nand.nand_fcr0,
@@ -785,7 +785,7 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
/* READID */
out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
out_be32(&ifc->ifc_nand.nand_fcr0,
--
1.7.9.5
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