> A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
> goes down. when the link goes down, Non-posted transactions issued
> via the ATMU requiring completion result in an instruction stall.
> At the same time a machine-check exception is generated to the core
> to allow further processing by the handler. We implements the handler
> which skips the instruction caused the stall.
Does skipping the faulting instruction really help?
We use the mpc83xx and have seen PCIe issues that may be
related to a documented errata in the CSB-PEX bridge (which
I can't find my copy of).
Do the 85xx and 83xx have the same PCIe block?
Recovery from it seems almost impossible - my interpretation
was that you have to hard reset the PCIe block and rewrite
the entire configuration.
The problem we see happens during some PEX DMA transfers
(possibly due to issues with the target), the DMA doesn't
complete and any further PIO transfers fault (and panic).
Unfortunately the PEX has no documented status registers,
so it is difficult to determine what is (or rather isn't)
Happening.
David
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