On Thu, Feb 16, 2012 at 05:50:47PM +0000, Tabi Timur-B04825 wrote:
> On Thu, Jan 26, 2012 at 2:58 PM, Ira W. Snyder <i...@ovro.caltech.edu> wrote:
> > The mpc8349ea has been observed to generate spurious end of segments
> > interrupts despite the fact that they are not enabled by this driver.
> > Check for them and ignore them to avoid a kernel error message.
>
> When this happens, are there any other status bits set? It seems
> weird that there are spurious interrupts from an internal block,
> especially since it's the same block on all 83xx parts.
>
> I wonder if the EOSI bit just happens to be set when the interrupt
> occurs for some other reason.
>
I'm not sure. The fsldma irq handler only prints bits it did not handle.
There are several other bits in the driver which should never be seen,
but they are handled by the irq handler anyway. This is just a remnant
from the original Freescale code.
I have a set of 15 test boards that I can use to figure out which other
bits are set when this happens, if it is important.
I put a variation of this patch (missing the "skip tasklet if not idle"
logic) into my production boards roughly a month ago. I've gotten the
"controller not idle" error message 748 times, as compared to the
"unhandled sr 0x00000002" message 3449 times.
This leads me to believe that this occurs mostly (but not always)
concurrent with the end-of-chain interrupt.
In the last month, the "unhandled sr" error has occurred on 92 out of
120 boards in production use. The statistics are included below. On some
boards, it is much more frequent than on others. All boards have roughly
the same workload.
Another interesting tidbit from my logs: this only occurs on DMA channel
2 (the are numbered starting at 0, it is the 3rd channel). Here is an
example log message:
[3484053.821689] of:fsl-elo-dma e00082a8.dma: chan2: irq: unhandled sr
0x00000002
Thanks,
Ira
15 serial-number-5
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