On Tue, Jan 31, 2012 at 09:58:22PM +0800, Shawn Guo wrote:
> On Tue, Jan 31, 2012 at 07:15:26AM -0600, Rob Herring wrote:
> ...
> > >> --- a/arch/arm/mach-mx5/imx51-dt.c
> > >> +++ b/arch/arm/mach-mx5/imx51-dt.c
> > >> @@ -47,7 +47,7 @@ static const struct of_dev_auxdata
> > >> imx51_auxdata_lookup[] __initconst = {
> > >> static int __init imx51_tzic_add_irq_domain(struct device_node *np,
> > >> struct device_node *interrupt_parent)
> > >> {
> > >> - irq_domain_add_simple(np, 0);
> > >> + irq_domain_add_legacy(np, 32, 0, 0, &irq_domain_simple_ops,
> > >> NULL);
> > >> return 0;
> > >> }
> > >>
> > >> @@ -57,7 +57,7 @@ static int __init imx51_gpio_add_irq_domain(struct
> > >> device_node *np,
> > >> static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
> > >>
> > >> gpio_irq_base -= 32;
> > >> - irq_domain_add_simple(np, gpio_irq_base);
> > >> + irq_domain_add_legacy(np, 32, gpio_irq_base, 0,
> > >> &irq_domain_simple_ops, NULL);
> > >
> > > The tzic on imx5 gets 128 irq lines rather than 32 here. The current
> > > code will make any hwirq that is > 32 hit the WARN_ON below in
> > > irq_domain_legacy_revmap().
> >
> > But this is the gpio controller code? Really this should be 4 domains,
> > but this temp fix is probably fine until you use my generic irq chip
> > support.
> >
> Sorry. The comment was put at the wrong place. It should be against
> imx51_tzic_add_irq_domain() just above.
I didn't know how large the bank was, so I just assumed 32. If it should
be 128 then I'll change it. Please confirm (or reply with a fixup patch)
g.
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