fsl_85xx_l2ctlr.o and fsl_85xx_cache_sram.o are built only
if CONFIG_FSL_85XX_CACHE_SRAM is defined. The driver that
qualifies and wants to make use of the CACHE SRAM's exported
API (i.e. a freescale net driver) should (be able to) select
this config option.
Signed-off-by: Claudiu Manoil <claudiu.man...@freescale.com>
---
arch/powerpc/platforms/85xx/Kconfig | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/Kconfig
b/arch/powerpc/platforms/85xx/Kconfig
index d7946be..6e2eecd 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -13,6 +13,15 @@ if FSL_SOC_BOOKE
if PPC32
+config FSL_85XX_CACHE_SRAM
+ bool
+ select PPC_LIB_RHEAP
+ help
+ When selected, this option enables cache-sram support
+ for memory allocation on P1/P2 QorIQ platforms.
+ cache-sram-size and cache-sram-offset kernel boot
+ parameters should be passed when this option is enabled.
+
config MPC8540_ADS
bool "Freescale MPC8540 ADS"
select DEFAULT_UIMAGE
--
1.6.6
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