On Thu, Nov 10, 2011 at 10:30:41AM -0600, Kumar Gala wrote: > On Nov 10, 2011, at 10:17 AM, Moffett, Kyle D wrote: > > Furthermore, it looks like there are a couple issues here I missed > > before. PPC64 systems all appear to have an L1_CACHE_SHIFT of 7, > > except when you turn on the P5020DS board option which magically > > changes it to "6" and breaks lord-knows-what. I think my patch > > series actually "breaks" that and makes e5500 use 7 as well. > > a value of '6' on E5500 / P5020DS is correct and doesn't break anything. > Setting it to 7 is wrong and thus the code is correct today. > > > Are you sure that a kernel built to support E5500 can also run on > > other 64-bit PowerPC/POWER systems? > > No it will not. There is not expectation of that as E5500 is an > embedded / Book-E class part and uses that ISA version. Book-S > (server) 64-bit machines are not OS compatible and we are not trying to > make them as such (but we do re-use a lot of code).
What about other 64-bit book3e chips? What cache block size does A2 have? -Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
