On Thu, Nov 10, 2011 at 07:40:04AM -0600, Kumar Gala wrote: > > On Nov 9, 2011, at 6:07 PM, Kyle Moffett wrote: > > > As FreeScale e500 systems have different cacheline sizes from e500mc, it > > is basically impossible for the kernel to support both in a single > > system image at present. > > > > Given that one is SPE-float and the other is classic-float, they are not > > generally userspace-compatible either. > > > > This patch updates the conditional to depend on whether the system is > > actually targetting an "e500" or "e500mc" core and entirely removes the > > unused sync-to-lwsync-replacement on e500v1/e500v2 systems. > > > > Signed-off-by: Kyle Moffett <kyle.d.moff...@boeing.com> > > --- > > arch/powerpc/include/asm/synch.h | 16 ++++------------ > > 1 files changed, 4 insertions(+), 12 deletions(-) > > Nak, we can run an e500mc in a mode that is compatible with e500v1/v2. I see > no reason to change the support we have there.
What "mode" do you mean? DCBZ32? We don't support using that currently, and I'd imagine the performance implication would be such that you'd never want to do it unless it's the only way to make some piece of legacy software work. > I see no reason to change the support we have there. No reason to remove complexity that is not needed, and is not planned to be needed? -Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
