Only build the setup functions when the corresponding entries are
included in the CPU table.
Signed-off-by: Kyle Moffett <kyle.d.moff...@boeing.com>
---
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 14 +++++++++++++-
1 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 8053db0..77721b2 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -17,6 +17,8 @@
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
+#if defined(CONFIG_FSL_E500_V1_V2) || defined(CONFIG_FSL_E500MC) \
+ || defined(CONFIG_FSL_E5500)
_GLOBAL(__e500_icache_setup)
mfspr r0, SPRN_L1CSR1
andi. r3, r0, L1CSR1_ICE
@@ -50,14 +52,18 @@ _GLOBAL(__e500_dcache_setup)
mtspr SPRN_L1CSR0, r0 /* Enable */
isync
blr
+#endif /* CONFIG_FSL_E500_V1_V2 || CONFIG_FSL_E500MC || CONFIG_FSL_E5500 */
-#ifdef CONFIG_PPC32
+#ifdef CONFIG_FSL_E200
_GLOBAL(__setup_cpu_e200)
/* enable dedicated debug exception handling resources (Debug APU) */
mfspr r3,SPRN_HID0
ori r3,r3,HID0_DAPUEN@l
mtspr SPRN_HID0,r3
b __setup_e200_ivors
+#endif
+
+#ifdef CONFIG_FSL_E500_V1_V2
_GLOBAL(__setup_cpu_e500v1)
_GLOBAL(__setup_cpu_e500v2)
mflr r4
@@ -72,6 +78,9 @@ _GLOBAL(__setup_cpu_e500v2)
#endif
mtlr r4
blr
+#endif
+
+#ifdef CONFIG_FSL_E500MC
_GLOBAL(__setup_cpu_e500mc)
mflr r4
bl __e500_icache_setup
@@ -80,7 +89,9 @@ _GLOBAL(__setup_cpu_e500mc)
mtlr r4
blr
#endif
+
/* Right now, restore and setup are the same thing */
+#ifdef CONFIG_FSL_E5500
_GLOBAL(__restore_cpu_e5500)
_GLOBAL(__setup_cpu_e5500)
mflr r4
@@ -96,3 +107,4 @@ _GLOBAL(__setup_cpu_e5500)
#endif
mtlr r4
blr
+#endif
--
1.7.2.5
_______________________________________________
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
