On Oct 25, 2011, at 5:54 PM, Matthew McClintock wrote:
> This is listed as a requirement after issuing a core reset to
> properly clear pending interrupts
>
Fix comment message to be more clear on 'what' this is required. [ its a
requirement on FSL corenet series / MPIC v4.x ]
> Signed-off-by: Matthew McClintock <m...@freescale.com>
> ---
> arch/powerpc/sysdev/mpic.c | 7 +++++++
> 1 files changed, 7 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
> index 9678081..f5b83f0 100644
> --- a/arch/powerpc/sysdev/mpic.c
> +++ b/arch/powerpc/sysdev/mpic.c
> @@ -1748,6 +1748,7 @@ void mpic_reset_core(int cpu)
> struct mpic *mpic = mpic_primary;
> u32 pir;
> int cpuid = get_hard_smp_processor_id(cpu);
> + int i;
>
> /* Set target bit for core reset */
> pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
> @@ -1759,6 +1760,12 @@ void mpic_reset_core(int cpu)
> pir &= ~(1 << cpuid);
> mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
> mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
> +
> + /* Perform 15 EOI on each reset core to clear pending interrupts */
> + for (i = 0; i < 15; i++) {
> + _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
> + MPIC_CPU_EOI, 0);
> + }
> }
> #endif /* CONFIG_SMP */
>
> --
> 1.7.6.1
>
>
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