Dan Malek <ppc6...@digitaldans.com> wrote on 2011/10/13 03:08:12:
>
>
> Hi Joakim.
>
> On Oct 12, 2011, at 2:36 PM, Joakim Tjernlund wrote:
>
> > Dan, where did you go? I figured you would throw yourself at this as
> > this is
> > something you been meaning to do yourself for years :)
>
> Too many things to do :-) I did have the wired page version that I've
> been using now and then.
ehhm, do the fun stuff first? :)
>
> I had the bad thought yesterday that we need to check the
> implementation for coherent memory. It appears we set the
> pages non-cached, which could cause some trouble. We
> have to ensure we never access the same physical page
> with different attributes from the 8M mapping and the single
> page "coherent" mapping.
>
> I'll try to get some testing done.
In 2.4 this seems fine:
#ifdef CONFIG_PIN_TLB
#define VMALLOC_OFFSET (0x2000000) /* 32M */
#else
#define VMALLOC_OFFSET (0x1000000) /* 16M */
#endif
...
/* adjust vmalloc_start */
vmalloc_start = (vmalloc_start + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1);
Earlier you have
MMU_init(void)
{
....
vmalloc_start = KERNELBASE + total_lowmem;
You could add 8MB to that just to be sure. In my system there is no
consistent_alloc so
early though.
Jocke
BTW, I noted that you can remove the
ori r11, r11, 1 /* Set valid bit in physical L2 page */
insns in the TLB routines in 3.0, the valid bit is now set be the mm system.
Jocke
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