[+linuxppc-dev] On Tue, Sep 6, 2011 at 11:00 AM, Paul E. McKenney <paul...@linux.vnet.ibm.com> wrote: > The trailing isync/lwsync in PowerPC value-returning atomics needs > to be a sync in order to provide the required ordering properties. > The leading lwsync/eieio can remain, as the remainder of the required > ordering guarantees are provided by the atomic instructions: Any > reordering will cause the stwcx to fail, which will result in a retry.
Admittedly, my powerpc barrier memory is starting to fade, but isn't isync sufficient here? It will make sure all instructions before it have retired, and will restart any speculative/issued instructions beyond it. lwsync not being sufficient makes sense since a load can overtake it. > diff --git a/arch/powerpc/include/asm/synch.h > b/arch/powerpc/include/asm/synch.h > index d7cab44..4d97fbe 100644 > --- a/arch/powerpc/include/asm/synch.h > +++ b/arch/powerpc/include/asm/synch.h > @@ -37,11 +37,7 @@ static inline void isync(void) > #endif > > #ifdef CONFIG_SMP > -#define __PPC_ACQUIRE_BARRIER \ > - START_LWSYNC_SECTION(97); \ > - isync; \ > - MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup); > -#define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER) > +#define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(sync;) This can just be done as "\n\tsync\n" instead of the stringify stuff. -Olof _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
