On Wed, 22 Jun 2011 09:55:36 -0500 Timur Tabi <ti...@freescale.com> wrote:
> Kumar Gala wrote: > >> > > >> > Well, not exactly. Paul wants to break that up since we're adding some > >> > primitive support for 201 HV mode too (for 970's). Last we discussed, > >> > the plan was to go for a generic HV mode bit and a separate bit for the > >> > version. > >> > > >> > Cheers, > >> > Ben. > > > Any ETA on Paul's intro of the FTR bit? If not I'll pull this into my > > 'next' tree and we can clean up later. > > Just FYI, this particular patch is because of a limitation in the Freescale > hypervisor. It's not because we're running in guest mode. If the hypervisor > provided full emulation of the timebase register, then we wouldn't need this > patch. The same can be said of KVM or any other hypervisor. >From Power ISA 2.06B, book III-E, section 9.2.1: Virtualized Implementation Note: In virtualized implementations, TBU and TBL are read-only. > So a generic HV mode bit is not going to help me, unless there's also a bit > that's specific to our hypervisor. And even then, we would need some way to > differentiate among different versions of our hypervisor, in case some future > version adds timebase support. That's very unlikely to happen. Ideally we would avoid doing this sync even when not running under a hypervisor, as long as firmware has done the sync, and kexec hasn't messed it up. Besides being a waste of boot time, the firmware's sync is probably tighter since it can use a platform-specific mechanism to start all the timebases at once. -Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
