Joakim Tjernlund/Transmode wrote on 2011/06/14 20:00:09: > From: Joakim Tjernlund/Transmode > > Dan Malek <ppc6...@digitaldans.com> wrote on 2011/06/14 18:06:45: > > > > > > Hi Joakim. > > > > On Jun 14, 2011, at 6:54 AM, Joakim Tjernlund wrote: > > > > > Various kernel asm modifies SRR0/SRR1 just before executing > > > a rfi. ..... > > > > I'm going to argue we can easily visually inspect for this > > since the code is static with just a couple of RFIs in these > > exception handlers. > > Yes, but then you also miss out on 8xx: Optimize ITLBMiss handler. > > > > > Some 8xx processors have few TLB entries, and always taking > > one for the kernel, especially if it isn't needed, could have a > > detrimental effect on the application performance. Even the > > "big" 8xx processors don't have that many entries. Some > > benchmarks run on an MPC850 would likely show this. > > I don't have a mpc850, do you? > > > > > Anyone making modifications to this level of software should > > know of this problem, or make it known in a comment. If you > > are making changes, just compile the code and manually > > check it with the couple of configuration options that affect > > the placement of the instructions. > > Very fragile but then again, not much are expected to change > in this area for 8xx.
So I checked and SRR0/SRR1 are fine w.r.t to head_8xx.S, it does not even come close. There are SRR0/SRR1 mods in entry.S too which works fine ATM. We don't have the same control of that file though. Could you check what impact pinning ITLB on 850 has? Jocke _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
