From: Michael Ellerman <mich...@ellerman.id.au>
On BOOK3E we don't have an SLB 0, but the equivalent concept is the
bolted entry mapping the kernel. Currently this is a 1G entry, so
for now hardcode that. This will probably need to be reworked in
future.
Signed-off-by: Michael Ellerman <mich...@ellerman.id.au>
---
arch/powerpc/kernel/setup_64.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 91a5cc5..3d0daf4 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -436,10 +436,14 @@ void __init setup_system(void)
static u64 slb0_limit(void)
{
+#ifdef CONFIG_PPC_BOOK3E
+ return 1 << 30;
+#else
if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
return 1UL << SID_SHIFT_1T;
}
return 1UL << SID_SHIFT;
+#endif
}
static void __init irqstack_early_init(void)
--
1.7.1
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