Hi,
I'm working on bring up for a new board based on Freescales p2020. I
have a programmable FPGA as a PCIe device with a buffer I can write to
and from.
I want to test performence for the PCIe bus.
I encountered a problem while doing a DMA between the FPGA & DDR.
The whole buffer moves to and from the device with out mismatches
but with low throughtput.
The thing is that the buffer divided to many transactions of byte size
instead of transferring it in a burst.
I must mention that even a buffer of word size, divided in to byte
transactions by the DMA (the core can read a word so it seems like the
DMA fault.
I tried to change the latency timer, max latency, min latency and cache
line in the configuration space of both sides of the pcie bus. It didn't
help.
Do you have an idea what can it be?
Thanks,
Natalie.
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