From: Ian Munsie <imun...@au1.ibm.com>
On the 44x we use 64bit page table entries, but the CPU is only 32bit.
When a PTE is loaded during a TLB miss each half is loaded into
different registers, so we need to reverse the offsets if the CPU is
running in little endian mode.
Signed-off-by: Ian Munsie <imun...@au1.ibm.com>
---
arch/powerpc/kernel/head_44x.S | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 6198733..d4c144f 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -258,8 +258,8 @@ interrupt_base:
/* Compute pte address */
rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
- lwz r11, 0(r12) /* Get high word of pte entry */
- lwz r12, 4(r12) /* Get low word of pte entry */
+ lwz r11, p64h(r12) /* Get high word of pte entry */
+ lwz r12, p64l(r12) /* Get low word of pte entry */
lis r10,tlb_44x_in...@ha
@@ -354,8 +354,8 @@ tlb_44x_patch_hwater_D:
/* Compute pte address */
rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
- lwz r11, 0(r12) /* Get high word of pte entry */
- lwz r12, 4(r12) /* Get low word of pte entry */
+ lwz r11, p64h(r12) /* Get high word of pte entry */
+ lwz r12, p64l(r12) /* Get low word of pte entry */
lis r10,tlb_44x_in...@ha
--
1.7.1
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