On Fri, Sep 10, 2010 at 08:14:44PM +0200, André Schwarz wrote: > > > At first I thought about registering 4 SPI busses representing the 4 cs# > > > lines and hide the cs# generation from the user. This would make > > > multiple cs# assertions for a single write impossible which is a very > > > useful feature. > > > > The SPI subsystem doesn't directly support this use-case. If you want > > to do this, then assign another chip select number for the purpose of > > enabling multiple CS lines at once... and be careful which drivers you > > allow to be bound to the oddball CS number. The in-kernel drivers > > certainly don't support this use-case, and care must be taken to > > ensure only one device is writing to the input line at a time. > > > > What specific hardware do you need this feature for? > > We have a board with multiple parallel video transmitters connected to > an FPGA. Video timing and general parameters are always the same and > there are quite a lot of settings to write during init/mode change. > > Doing this in parallel will speed things up significantly.
Yeah; Then I would handle it as a separate cs# and map it to enabling multiple CS lines at a time. > BTW: would "drivers/misc" be a proper location ? > Who's supposed to pick that driver up and on what list shall I post it > for review ? You should cc spi-devel-general, and feel free to cc me. drivers/misc would probably be an okay place for it to live; but if it only appears on a single machine, then it may make more sense in arch/*/<board-directory>. What arch or SoC is this running on? g. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
