This adds support for programming the data processing FPGAs on the OVRO
CARMA board. These FPGAs have a special programming sequence that
requires that we program the Freescale DMA engine, which is only
available inside the kernel.
Signed-off-by: Ira W. Snyder <i...@ovro.caltech.edu>
---
drivers/fpga/carma/Kconfig | 8 +
drivers/fpga/carma/Makefile | 1 +
drivers/fpga/carma/carma-fpga-program.c | 1136 +++++++++++++++++++++++++++++++
3 files changed, 1145 insertions(+), 0 deletions(-)
create mode 100644 drivers/fpga/carma/carma-fpga-program.c
diff --git a/drivers/fpga/carma/Kconfig b/drivers/fpga/carma/Kconfig
index 5592f73..c9df01a 100644
--- a/drivers/fpga/carma/Kconfig
+++ b/drivers/fpga/carma/Kconfig
@@ -27,4 +27,12 @@ config CARMA_FPGA
Say Y here to include support for communicating with the data
processing FPGAs on the CARMA board.
+config CARMA_FPGA_PROGRAM
+ tristate "CARMA DATA-FPGA Programmer"
+ depends on CARMA
+ default n
+ help
+ Say Y here to include support for programming the data processing
+ FPGAs on the CARMA board.
+
endif # FPGA_DRIVERS
diff --git a/drivers/fpga/carma/Makefile b/drivers/fpga/carma/Makefile
index c175d34..4948bbb 100644
--- a/drivers/fpga/carma/Makefile
+++ b/drivers/fpga/carma/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_CARMA) += carma.o
obj-$(CONFIG_CARMA_FPGA) += carma-fpga.o
+obj-$(CONFIG_CARMA_FPGA_PROGRAM) += carma-fpga-program.o
diff --git a/drivers/fpga/carma/carma-fpga-program.c
b/drivers/fpga/carma/carma-fpga-program.c
new file mode 100644
index 0000000..04dc115
--- /dev/null
+++ b/drivers/fpga/carma/carma-fpga-program.c
@@ -0,0 +1,1136 @@
+/*
+ * CARMA Board DATA-FPGA Programmer
+ *
+ * Copyright (c) 2009-2010 Ira W. Snyder <i...@ovro.caltech.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/cdev.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/highmem.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/leds.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_platform.h>
+#include <linux/dmaengine.h>
+
+/* Freescale DMA Controller DMA_SLAVE interface */
+#include <asm/fsldma.h>
+
+/* MPC8349EMDS specific get_immrbase() */
+#include <sysdev/fsl_soc.h>
+
+/* CARMA device class */
+#include "carma.h"
+
+static const char drv_name[] = "carma-fpga-program";
+
+/*
+ * Maximum firmware size
+ *
+ * 12849552 bytes for a CARMA Digitizer Board
+ * 18662880 bytes for a CARMA Correlator Board
+ */
+#define FW_SIZE_EP2S90 12849552
+#define FW_SIZE_EP2S130 18662880
+
+struct fpga_fw_elem {
+ struct page *page;
+ unsigned int len;
+ struct list_head entry;
+};
+
+struct fpga_dev {
+
+ /* Character Device */
+ struct cdev cdev;
+ dev_t devno;
+
+ /* Device Registers */
+ struct device *dev;
+ void __iomem *regs;
+ void __iomem *immr;
+
+ /* Freescale DMA Device */
+ struct device *dmadev;
+ struct dma_chan *chan;
+
+ /* Interrupts */
+ int irq, status;
+ struct completion completion;
+
+ /* FPGA Bitfile */
+ struct mutex lock;
+ struct list_head list;
+ size_t bytes;
+
+ size_t fw_size;
+};
+
+#define to_fpga_dev(X) container_of(X, struct fpga_dev, cdev)
+
+/*
+ * FPGA Bitfile Element Allocation Helpers
+ */
+
+static struct fpga_fw_elem *fpga_fw_elem_alloc(gfp_t gfp)
+{
+ struct fpga_fw_elem *elem;
+
+ elem = kzalloc(sizeof(*elem), gfp);
+ if (!elem)
+ return NULL;
+
+ elem->page = alloc_page(gfp);
+ if (!elem->page) {
+ kfree(elem);
+ return NULL;
+ }
+
+ INIT_LIST_HEAD(&elem->entry);
+ return elem;
+}
+
+static void fpga_fw_elem_free(struct fpga_fw_elem *elem)
+{
+ if (elem) {
+ __free_page(elem->page);
+ kfree(elem);
+ }
+}
+
+/*
+ * FPGA Bitfile Helpers
+ */
+
+/*
+ * Drop the firmware bitfile image from memory
+ *
+ * LOCKING: you must hold the priv->lock mutex
+ *
+ * @param priv the driver's private data structure
+ */
+static void fpga_drop_firmware_data(struct fpga_dev *priv)
+{
+ struct fpga_fw_elem *elem, *tmp;
+
+ priv->bytes = 0;
+ list_for_each_entry_safe(elem, tmp, &priv->list, entry) {
+ list_del(&elem->entry);
+ fpga_fw_elem_free(elem);
+ }
+}
+
+static unsigned int list_num_entries(struct list_head *list)
+{
+ struct list_head *tmp;
+ unsigned int num = 0;
+
+ list_for_each(tmp, list)
+ num++;
+
+ return num;
+}
+
+/*
+ * LED Trigger (could be a seperate module)
+ */
+
+/*
+ * NOTE: this whole thing does have the problem that whenever the led's are
+ * NOTE: first set to use the fpga trigger, they could be in the wrong state
+ */
+
+DEFINE_LED_TRIGGER(ledtrig_fpga);
+
+static void ledtrig_fpga_programmed(bool enabled)
+{
+ if (enabled)
+ led_trigger_event(ledtrig_fpga, LED_FULL);
+ else
+ led_trigger_event(ledtrig_fpga, LED_OFF);
+}
+
+/*
+ * FPGA Register Helpers
+ */
+
+/* Register Definitions */
+#define FPGA_CONFIG_CONTROL 0x40
+#define FPGA_CONFIG_STATUS 0x44
+#define FPGA_CONFIG_FIFO_SIZE 0x48
+#define FPGA_CONFIG_FIFO_USED 0x4C
+#define FPGA_CONFIG_TOTAL_BYTE_COUNT 0x50
+#define FPGA_CONFIG_CUR_BYTE_COUNT 0x54
+
+#define FPGA_FIFO_ADDRESS 0x3000
+
+static int fpga_fifo_size(void __iomem *regs)
+{
+ return ioread32be(regs + FPGA_CONFIG_FIFO_SIZE);
+}
+
+static int fpga_config_error(void __iomem *regs)
+{
+ return ioread32be(regs + FPGA_CONFIG_STATUS) & 0xFFFE;
+}
+
+static int fpga_fifo_empty(void __iomem *regs)
+{
+ return ioread32be(regs + FPGA_CONFIG_FIFO_USED) == 0;
+}
+
+static void fpga_fifo_write(void __iomem *regs, u32 val)
+{
+ iowrite32be(val, regs + FPGA_FIFO_ADDRESS);
+}
+
+static void fpga_set_byte_count(void __iomem *regs, u32 count)
+{
+ iowrite32be(count, regs + FPGA_CONFIG_TOTAL_BYTE_COUNT);
+}
+
+static void fpga_programmer_enable(struct fpga_dev *priv, bool dma)
+{
+ if (dma)
+ iowrite32be(0x5, priv->regs + FPGA_CONFIG_CONTROL);
+ else
+ iowrite32be(0x1, priv->regs + FPGA_CONFIG_CONTROL);
+}
+
+static void fpga_programmer_disable(struct fpga_dev *priv)
+{
+ iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL);
+}
+
+static void fpga_dump_registers(struct fpga_dev *priv)
+{
+ /* good status: do nothing */
+ if (priv->status == 0)
+ return;
+
+ /* Dump all status registers */
+ dev_err(priv->dev, "Configuration failed, dumping status registers\n");
+ dev_err(priv->dev, "Control: 0x%.8x\n", ioread32be(priv->regs +
FPGA_CONFIG_CONTROL));
+ dev_err(priv->dev, "Status: 0x%.8x\n", ioread32be(priv->regs +
FPGA_CONFIG_STATUS));
+ dev_err(priv->dev, "FIFO Size: 0x%.8x\n", ioread32be(priv->regs +
FPGA_CONFIG_FIFO_SIZE));
+ dev_err(priv->dev, "FIFO Used: 0x%.8x\n", ioread32be(priv->regs +
FPGA_CONFIG_FIFO_USED));
+ dev_err(priv->dev, "FIFO Total: 0x%.8x\n", ioread32be(priv->regs +
FPGA_CONFIG_TOTAL_BYTE_COUNT));
+ dev_err(priv->dev, "FIFO Curr: 0x%.8x\n", ioread32be(priv->regs +
FPGA_CONFIG_CUR_BYTE_COUNT));
+}
+
+/*
+ * FPGA Power Supply Code
+ */
+
+#define CTL_PWR_CONTROL 0x2006
+#define CTL_PWR_STATUS 0x200A
+#define CTL_PWR_FAIL 0x200B
+
+/*
+ * Determine if the FPGA power is good for all supplies
+ */
+static bool fpga_power_good(struct fpga_dev *priv)
+{
+ u8 val;
+
+ val = ioread8(priv->regs + CTL_PWR_STATUS);
+ if (val & 0x10)
+ return false;
+
+ return val == 0x0F;
+}
+
+/*
+ * Disable the FPGA power supplies
+ */
+static void fpga_disable_power_supplies(struct fpga_dev *priv)
+{
+ unsigned long start;
+ u8 val;
+
+ iowrite8(0x00, priv->regs + CTL_PWR_CONTROL);
+
+ /*
+ * Wait 500ms for the power rails to discharge
+ *
+ * Without this delay, the CTL-CPLD state machine can get into a
+ * state where it is waiting for the power-goods to assert, but they
+ * never do. This only happens when enabling and disabling the
+ * power sequencer very rapidly.
+ *
+ * The loop below will also wait for the power goods to de-assert,
+ * but testing has shown that they are always disabled by the time
+ * the sleep completes. However, omitting the sleep and only waiting
+ * for the power-goods to de-assert was not sufficient to ensure
+ * that the power sequencer would not wedge itself.
+ */
+ msleep(500);
+
+ start = jiffies;
+ while (time_before(jiffies, start + HZ)) {
+ val = ioread8(priv->regs + CTL_PWR_STATUS);
+ if (!(val & 0x0f))
+ break;
+
+ msleep(10);
+ }
+
+ val = ioread8(priv->regs + CTL_PWR_STATUS);
+ if (val & 0x0f) {
+ dev_err(priv->dev, "power disable failed: "
+ "power goods: status 0x%.2x\n", val);
+ }
+
+ if (val & 0x10) {
+ dev_err(priv->dev, "power disable failed: "
+ "alarm bit set: status 0x%.2x\n", val);
+ }
+}
+
+/*
+ * Enable the FPGA power supplies, waiting up to 1 second
+ * for them to enable successfully.
+ *
+ * @return 0 if the power went good, -ERRNO otherwise
+ */
+static int fpga_enable_power_supplies(struct fpga_dev *priv)
+{
+ unsigned long start = jiffies;
+
+ if (fpga_power_good(priv)) {
+ dev_dbg(priv->dev, "power was already good\n");
+ return 0;
+ }
+
+ iowrite8(0x01, priv->regs + CTL_PWR_CONTROL);
+ while (time_before(jiffies, start + HZ)) {
+ if (fpga_power_good(priv))
+ return 0;
+
+ msleep(10);
+ }
+
+ return fpga_power_good(priv) ? 0 : -EBUSY;
+}
+
+/*
+ * Determine if the FPGA power supplies are all enabled
+ */
+static bool fpga_power_enabled(struct fpga_dev *priv)
+{
+ u8 val;
+
+ val = ioread8(priv->regs + CTL_PWR_CONTROL);
+ if (val & 0x01)
+ return true;
+
+ return false;
+}
+
+/*
+ * Determine if the FPGA's are programmed and running correctly
+ */
+static bool fpga_running(struct fpga_dev *priv)
+{
+ if (!fpga_power_good(priv))
+ return false;
+
+ /* Check the config done bit */
+ return ioread32be(priv->regs + FPGA_CONFIG_STATUS) & (1 << 18);
+}
+
+/*
+ * FPGA Programming Code
+ */
+
+/*
+ * Program some data to the FPGA fifo
+ *
+ * @priv the private data
+ * @buf the data to program
+ * @count the length of data to program (must be a multiple of 4 bytes)
+ *
+ * @return 0 on success, -ERRNO otherwise
+ */
+static int fpga_program_block(struct fpga_dev *priv, void *buf, size_t count)
+{
+ u32 *data = buf;
+ int size = fpga_fifo_size(priv->regs);
+ int i, len;
+ unsigned long timeout;
+
+ /* FIXME: BUG_ON instead */
+ WARN_ON_ONCE(count % 4 != 0);
+
+ while (count > 0) {
+
+ /* Get the size of the block to write (maximum is FIFO_SIZE) */
+ len = min_t(size_t, count, size);
+ timeout = jiffies + HZ / 4;
+
+ /* Write the block */
+ for (i = 0; i < len / 4; i++)
+ fpga_fifo_write(priv->regs, data[i]);
+
+ /* Update the amounts left */
+ count -= len;
+ data += len / 4;
+
+ /* Wait for the fifo to empty */
+ while (true) {
+
+ if (fpga_fifo_empty(priv->regs)) {
+ break;
+ } else {
+ dev_dbg(priv->dev, "Fifo not empty\n");
+ cpu_relax();
+ }
+
+ if (fpga_config_error(priv->regs)) {
+ dev_err(priv->dev, "Error detected\n");
+ return -EIO;
+ }
+
+ if (time_after(jiffies, timeout)) {
+ dev_err(priv->dev, "Fifo timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ msleep(10);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * Program the FPGA's using the CPU
+ *
+ * @param priv the driver's private data structure
+ * @return 0 on success, -ERRNO otherwise
+ */
+static noinline int fpga_program_cpu(struct fpga_dev *priv)
+{
+ struct fpga_fw_elem *elem;
+ void *data;
+ int ret;
+
+ /* Disable the programmer */
+ fpga_programmer_disable(priv);
+
+ /* Set the total byte count */
+ fpga_set_byte_count(priv->regs, priv->bytes);
+ dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes);
+
+ /* Enable the controller for programming */
+ fpga_programmer_enable(priv, false);
+ dev_dbg(priv->dev, "enabled the controller\n");
+
+ /* Write each chunk of the FPGA bitfile to FPGA programmer */
+ list_for_each_entry(elem, &priv->list, entry) {
+ data = kmap(elem->page);
+ ret = fpga_program_block(priv, data, elem->len);
+ kunmap(elem->page);
+
+ if (ret)
+ goto out_disable_controller;
+ }
+
+ /* Wait for the interrupt handler to notify us that programming
finished */
+ ret = wait_for_completion_timeout(&priv->completion, 2 * HZ);
+ if (!ret) {
+ dev_err(priv->dev, "Timed out waiting for completion\n");
+ ret = -ETIMEDOUT;
+ goto out_disable_controller;
+ }
+
+ /* Retrieve the status from the interrupt handler */
+ ret = priv->status;
+
+out_disable_controller:
+ fpga_programmer_disable(priv);
+ return ret;
+}
+
+/*
+ * Program the FPGA's using the DMA controller
+ *
+ * @param priv the driver's private data structure
+ * @return 0 on success, -ERRNO otherwise
+ */
+static noinline int fpga_program_dma(struct fpga_dev *priv)
+{
+ struct dma_chan *chan = priv->chan;
+ struct dma_async_tx_descriptor *tx;
+ struct fsl_dma_slave *slave;
+ struct sg_table table;
+ dma_cookie_t cookie;
+ unsigned int nents, npages;
+ size_t len, avail = 0;
+ int ret;
+ struct scatterlist *sg;
+ struct fpga_fw_elem *elem;
+
+ /* Disable the programmer */
+ fpga_programmer_disable(priv);
+ //chan->device->device_terminate_all(chan);
+
+ /* Allocate the DMA_SLAVE structure */
+ slave = fsl_dma_slave_alloc(GFP_KERNEL);
+ if (!slave) {
+ dev_err(priv->dev, "Unable to allocate DMA_SLAVE structure\n");
+ ret = -ENOMEM;
+ goto out_return;
+ }
+
+ /* Set the DMA controller in external start mode */
+ slave->external_start = true;
+ slave->request_count = 8 * 32;
+
+ /* Allocate the SG table */
+ npages = list_num_entries(&priv->list);
+ ret = sg_alloc_table(&table, npages, GFP_KERNEL);
+ if (ret) {
+ dev_err(priv->dev, "Unable to allocate SG table\n");
+ goto out_free_slave;
+ }
+
+ /* Fill the SG table */
+ sg = table.sgl;
+ list_for_each_entry(elem, &priv->list, entry) {
+ sg_set_page(sg, elem->page, elem->len, 0);
+ sg = sg_next(sg);
+ }
+
+ /* Map the SG table for DMA */
+ nents = dma_map_sg(priv->dmadev, table.sgl, npages, DMA_TO_DEVICE);
+ if (nents <= 0) {
+ dev_err(priv->dev, "Unable to DMA map SG table\n");
+ ret = -ENOMEM;
+ goto out_free_table;
+ }
+
+ /* Append the addresses to the DMA_SLAVE structure */
+ avail = priv->bytes;
+ while (avail > 0) {
+ len = min_t(size_t, avail, PAGE_SIZE);
+ ret = fsl_dma_slave_append(slave, 0xf0003000, len);
+ if (ret) {
+ dev_err(priv->dev, "Unable to append FIFO address\n");
+ goto out_unmap_table;
+ }
+
+ avail -= len;
+ }
+
+ /* Submit the DMA slave */
+ chan->private = slave;
+ tx = chan->device->device_prep_slave_sg(chan, table.sgl, nents,
+ DMA_TO_DEVICE, 0);
+ if (!tx) {
+ dev_err(priv->dev, "Unable to prep DMA_SLAVE transaction\n");
+ ret = -ENOMEM;
+ goto out_unmap_table;
+ }
+
+ /*
+ * Submit the transaction to the DMA controller
+ *
+ * We would leak memory if the submission failed, but that doesn't
+ * happen in the fsldma driver, so it isn't an issue
+ */
+ cookie = tx->tx_submit(tx);
+ if (dma_submit_error(cookie)) {
+ dev_err(priv->dev, "Unable to submit DMA_SLAVE transaction\n");
+ ret = -ENOMEM;
+ goto out_unmap_table;
+ }
+
+ dma_async_memcpy_issue_pending(chan);
+
+ /* Set the total byte count */
+ fpga_set_byte_count(priv->regs, priv->bytes);
+ dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes);
+
+ /* Enable the controller for DMA programming */
+ fpga_programmer_enable(priv, true);
+ dev_dbg(priv->dev, "enabled the controller\n");
+
+ /* Wait for the interrupt handler to notify us that programming
finished */
+ ret = wait_for_completion_timeout(&priv->completion, 2 * HZ);
+ if (!ret) {
+ dev_err(priv->dev, "Timed out waiting for completion\n");
+ ret = -ETIMEDOUT;
+ goto out_disable_controller;
+ }
+
+ /* Retrieve the status from the interrupt handler */
+ ret = priv->status;
+
+out_disable_controller:
+ fpga_programmer_disable(priv);
+ //chan->device->device_terminate_all(chan);
+out_unmap_table:
+ dma_unmap_sg(priv->dmadev, table.sgl, npages, DMA_TO_DEVICE);
+out_free_table:
+ sg_free_table(&table);
+out_free_slave:
+ fsl_dma_slave_free(slave);
+out_return:
+ return ret;
+}
+
+/*
+ * Interrupt Handling
+ */
+
+static irqreturn_t fpga_interrupt(int irq, void *dev_id)
+{
+ struct fpga_dev *priv = dev_id;
+
+ /* Save the status */
+ priv->status = fpga_config_error(priv->regs) ? -EIO : 0;
+ dev_dbg(priv->dev, "INTERRUPT status %d\n", priv->status);
+ fpga_dump_registers(priv);
+
+ /* Disabling the programmer clears the interrupt */
+ fpga_programmer_disable(priv);
+
+ /* Notify any waiters */
+ complete(&priv->completion);
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * SYSFS Helpers
+ */
+
+/*
+ * Reset the FPGA's, deconfiguring them
+ *
+ * LOCKING: priv->lock mutex must be held
+ */
+static int fpga_do_stop(struct fpga_dev *priv)
+{
+ /* Set the led to unprogrammed */
+ ledtrig_fpga_programmed(false);
+
+ /* Pulse the config line to reset the FPGA's */
+ iowrite32be(0x3, priv->regs + FPGA_CONFIG_CONTROL);
+ iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL);
+
+ return 0;
+}
+
+static noinline int fpga_do_program(struct fpga_dev *priv)
+{
+ int ret;
+
+ if (list_empty(&priv->list)) {
+ dev_err(priv->dev, "No data to program\n");
+ return -EINVAL;
+ }
+
+ if (priv->bytes != priv->fw_size) {
+ dev_err(priv->dev, "Incorrect bitfile size: got %zu bytes, "
+ "should be %zu bytes\n",
+ priv->bytes, priv->fw_size);
+ return -EINVAL;
+ }
+
+ if (!fpga_power_enabled(priv)) {
+ dev_err(priv->dev, "Power not enabled\n");
+ return -EINVAL;
+ }
+
+ if (!fpga_power_good(priv)) {
+ dev_err(priv->dev, "Power not good\n");
+ return -EINVAL;
+ }
+
+ /* Set the LED to unprogrammed */
+ ledtrig_fpga_programmed(false);
+
+ /* Try to program the FPGA's using DMA */
+ ret = fpga_program_dma(priv);
+
+ /* If DMA failed or doesn't exist, try with CPU */
+ if (ret) {
+ dev_warn(priv->dev, "Falling back to CPU programming\n");
+ ret = fpga_program_cpu(priv);
+ }
+
+ if (ret) {
+ dev_err(priv->dev, "Unable to program FPGA's\n");
+ return ret;
+ }
+
+ /* Drop the firmware bitfile from memory */
+ fpga_drop_firmware_data(priv);
+
+ dev_dbg(priv->dev, "FPGA programming successful\n");
+ ledtrig_fpga_programmed(true);
+
+ return 0;
+}
+
+/*
+ * File Operations
+ */
+
+static int fpga_open(struct inode *inode, struct file *filp)
+{
+ struct fpga_dev *priv = to_fpga_dev(inode->i_cdev);
+
+ /* We only allow one process at a time */
+ if (mutex_lock_interruptible(&priv->lock))
+ return -ERESTARTSYS;
+
+ filp->private_data = priv;
+
+ /* Free any data left over from a previous open (if any) */
+ fpga_drop_firmware_data(priv);
+
+ return nonseekable_open(inode, filp);
+}
+
+static int fpga_release(struct inode *inode, struct file *filp)
+{
+ struct fpga_dev *priv = filp->private_data;
+
+ mutex_unlock(&priv->lock);
+ return 0;
+}
+
+static ssize_t fpga_write(struct file *filp, const char __user *buf,
+ size_t count, loff_t *f_pos)
+{
+ struct fpga_dev *priv = filp->private_data;
+ struct fpga_fw_elem *elem, *tmp;
+ size_t used, len, copy;
+ struct list_head list;
+ void *mem;
+ int ret;
+
+ /* Disallow firmware images larger than 16MB */
+ if (priv->bytes >= priv->fw_size)
+ return -ENOSPC;
+
+ count = min_t(size_t, priv->fw_size - priv->bytes, count);
+
+ INIT_LIST_HEAD(&list);
+ len = count;
+ used = 0;
+
+ while (len > 0) {
+
+ /* Allocate a list element */
+ elem = fpga_fw_elem_alloc(GFP_KERNEL);
+ if (!elem) {
+ count = used;
+ goto out_success;
+ }
+
+ /* Copy the data from userspace */
+ copy = min_t(size_t, PAGE_SIZE, len);
+ mem = kmap(elem->page);
+ ret = copy_from_user(mem, buf + used, copy);
+ kunmap(elem->page);
+
+ if (ret) {
+ count = -EFAULT;
+ goto out_cleanup;
+ }
+
+ elem->len = copy;
+ list_add_tail(&elem->entry, &list);
+
+ len -= copy;
+ used += copy;
+ }
+
+out_success:
+ if (list_empty(&list))
+ return -ENOMEM;
+
+ list_splice_tail_init(&list, &priv->list);
+ priv->bytes += count;
+
+ *f_pos += count;
+ return count;
+
+out_cleanup:
+ /* Free the last allocated element */
+ fpga_fw_elem_free(elem);
+
+ /* Free all of the elements on the temporary list */
+ list_for_each_entry_safe(elem, tmp, &list, entry) {
+ list_del(&elem->entry);
+ fpga_fw_elem_free(elem);
+ }
+
+ return count;
+}
+
+static const struct file_operations fpga_fops = {
+ .open = fpga_open,
+ .release = fpga_release,
+ .write = fpga_write,
+ .llseek = no_llseek,
+};
+
+/*
+ * Device Attributes
+ */
+
+static ssize_t pfail_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct fpga_dev *priv = dev_get_drvdata(dev);
+ u8 val;
+
+ val = ioread8(priv->regs + CTL_PWR_FAIL);
+ return snprintf(buf, PAGE_SIZE, "0x%.2x\n", val);
+}
+
+static ssize_t pgood_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct fpga_dev *priv = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_good(priv));
+}
+
+static ssize_t penable_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct fpga_dev *priv = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_enabled(priv));
+}
+
+static ssize_t penable_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct fpga_dev *priv = dev_get_drvdata(dev);
+ unsigned long val;
+ int ret;
+
+ if (strict_strtoul(buf, 0, &val))
+ return -EINVAL;
+
+ if (val) {
+ ret = fpga_enable_power_supplies(priv);
+ if (ret)
+ return ret;
+ } else {
+ fpga_do_stop(priv);
+ fpga_disable_power_supplies(priv);
+ }
+
+ return count;
+}
+
+static ssize_t program_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct fpga_dev *priv = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%d\n", fpga_running(priv));
+}
+
+static ssize_t program_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct fpga_dev *priv = dev_get_drvdata(dev);
+ unsigned long val;
+ int ret;
+
+ if (strict_strtoul(buf, 0, &val))
+ return -EINVAL;
+
+ /* We can't have an image writer and be programming simultaneously */
+ if (mutex_lock_interruptible(&priv->lock))
+ return -ERESTARTSYS;
+
+ /* Program or Reset the FPGA's */
+ ret = val ? fpga_do_program(priv) : fpga_do_stop(priv);
+ if (ret)
+ goto out_unlock;
+
+ /* Success */
+ ret = count;
+
+out_unlock:
+ mutex_unlock(&priv->lock);
+ return ret;
+}
+
+static DEVICE_ATTR(power_fail, S_IRUGO, pfail_show, NULL);
+static DEVICE_ATTR(power_good, S_IRUGO, pgood_show, NULL);
+static DEVICE_ATTR(power_enable, S_IRUGO | S_IWUGO, penable_show,
penable_store);
+static DEVICE_ATTR(program, S_IRUGO | S_IWUGO, program_show, program_store);
+
+static struct attribute *fpga_attributes[] = {
+ &dev_attr_power_fail.attr,
+ &dev_attr_power_good.attr,
+ &dev_attr_power_enable.attr,
+ &dev_attr_program.attr,
+ NULL,
+};
+
+static const struct attribute_group fpga_attr_group = {
+ .attrs = fpga_attributes,
+};
+
+/*
+ * OpenFirmware Device Subsystem
+ */
+
+#define SYS_REG_VERSION 0x00
+#define SYS_REG_GEOGRAPHIC 0x10
+
+static bool dma_filter(struct dma_chan *chan, void *data)
+{
+ /*
+ * DMA Channel #0 is the only acceptable device
+ *
+ * This probably won't survive an unload/load cycle of the Freescale
+ * DMAEngine driver, but that won't be a problem
+ */
+ return chan->chan_id == 0 && chan->device->dev_id == 0;
+}
+
+static int fpga_of_remove(struct platform_device *op)
+{
+ struct fpga_dev *priv = dev_get_drvdata(&op->dev);
+
+ sysfs_remove_group(&priv->dev->kobj, &fpga_attr_group);
+
+ cdev_del(&priv->cdev);
+ free_irq(priv->irq, priv);
+
+ iounmap(priv->immr);
+
+ fpga_disable_power_supplies(priv);
+ iounmap(priv->regs);
+
+ dma_release_channel(priv->chan);
+ carma_device_destroy(priv->devno);
+ unregister_chrdev_region(priv->devno, 1);
+
+ /* Free any firmware image that has not been programmed */
+ fpga_drop_firmware_data(priv);
+
+ mutex_destroy(&priv->lock);
+ kfree(priv);
+
+ return 0;
+}
+
+static int fpga_of_probe(struct platform_device *op, const struct of_device_id
*match)
+{
+ struct device_node *of_node = op->dev.of_node;
+ struct fpga_dev *priv;
+ dma_cap_mask_t mask;
+ u32 ver;
+ int ret;
+
+ /* Allocate private data */
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(&op->dev, "Unable to allocate private data\n");
+ ret = -ENOMEM;
+ goto out_return;
+ }
+
+ dev_set_drvdata(&op->dev, priv);
+ mutex_init(&priv->lock);
+ init_completion(&priv->completion);
+ cdev_init(&priv->cdev, &fpga_fops);
+ priv->dmadev = &op->dev;
+ INIT_LIST_HEAD(&priv->list);
+
+ /* Allocate the character device */
+ ret = alloc_chrdev_region(&priv->devno, 0, 1, drv_name);
+ if (ret) {
+ dev_err(&op->dev, "Unable to allocate chardev region\n");
+ goto out_free_priv;
+ }
+
+ /* Allocate the CARMA device */
+ priv->dev = carma_device_create(&op->dev, priv->devno, drv_name);
+ if (IS_ERR(priv->dev)) {
+ dev_err(&op->dev, "Unable to create CARMA device\n");
+ ret = PTR_ERR(priv->dev);
+ goto out_unregister_chrdev_region;
+ }
+
+ dev_set_drvdata(priv->dev, priv);
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_MEMCPY, mask);
+ dma_cap_set(DMA_INTERRUPT, mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ /* Get control of DMA channel #0 */
+ priv->chan = dma_request_channel(mask, dma_filter, NULL);
+ if (!priv->chan) {
+ dev_err(&op->dev, "Unable to acquire DMA channel #0\n");
+ ret = -ENODEV;
+ goto out_carma_device_destroy;
+ }
+
+ /* Remap the registers for use */
+ priv->regs = of_iomap(of_node, 0);
+ if (!priv->regs) {
+ dev_err(&op->dev, "Unable to ioremap registers\n");
+ ret = -ENOMEM;
+ goto out_dma_release_channel;
+ }
+
+ /* Remap the IMMR for use */
+ priv->immr = ioremap(get_immrbase(), 0x100000);
+ if (!priv->immr) {
+ dev_err(&op->dev, "Unable to ioremap IMMR\n");
+ ret = -ENOMEM;
+ goto out_unmap_regs;
+ }
+
+ /*
+ * Check that external DMA is configured
+ *
+ * U-Boot does this for us, but we should check it and bail out if
+ * there is a problem. Failing to have this register setup correctly
+ * will cause the DMA controller to transfer a single cacheline
+ * worth of data, then wedge itself.
+ */
+ if ((ioread32be(priv->immr + 0x114) & 0xE00) != 0xE00) {
+ dev_err(&op->dev, "External DMA control not configured\n");
+ ret = -ENODEV;
+ goto out_unmap_immr;
+ }
+
+ /*
+ * Check the CTL-CPLD version
+ *
+ * This drivers uses the CTL-CPLD DATA-FPGA power sequencer, and we
+ * don't want to run on any version of the CTL-CPLD that does not use
+ * a compatible register layout.
+ *
+ * v2: changed register layout, added power sequencer
+ * v3: added glitch filter on the i2c overcurrent/overtemp outputs
+ */
+ ver = ioread8(priv->regs + 0x2000);
+ if (ver != 0x02 && ver != 0x03) {
+ dev_err(&op->dev, "CTL-CPLD is not version 0x02 or 0x03!\n");
+ ret = -ENODEV;
+ goto out_unmap_immr;
+ }
+
+ /*
+ * Set the exact size that the firmware image should be
+ */
+ ver = ioread32be(priv->regs + SYS_REG_VERSION);
+ priv->fw_size = (ver & (1 << 18)) ? FW_SIZE_EP2S130 : FW_SIZE_EP2S90;
+
+ /* Find the correct IRQ number */
+ priv->irq = irq_of_parse_and_map(of_node, 0);
+ ret = request_irq(priv->irq, fpga_interrupt, IRQF_SHARED, drv_name,
priv);
+ if (ret) {
+ dev_err(&op->dev, "Unable to request IRQ %d\n", priv->irq);
+ ret = -ENODEV;
+ goto out_unmap_immr;
+ }
+
+ /* Reset and stop the FPGA's, just in case */
+ fpga_do_stop(priv);
+
+ /* Register the character device */
+ ret = cdev_add(&priv->cdev, priv->devno, 1);
+ if (ret) {
+ dev_err(&op->dev, "Unable to add character device\n");
+ goto out_free_irq;
+ }
+
+ /* Create the sysfs files */
+ ret = sysfs_create_group(&priv->dev->kobj, &fpga_attr_group);
+ if (ret) {
+ dev_err(&op->dev, "Unable to create sysfs files\n");
+ goto out_cdev_del;
+ }
+
+ dev_info(priv->dev, "CARMA FPGA Programmer: %s rev%s with %s FPGAs\n",
+ (ver & (1 << 17)) ? "Correlator" : "Digitizer",
+ (ver & (1 << 16)) ? "B" : "A",
+ (ver & (1 << 18)) ? "EP2S130" : "EP2S90");
+
+ return 0;
+
+out_cdev_del:
+ cdev_del(&priv->cdev);
+out_free_irq:
+ free_irq(priv->irq, priv);
+out_unmap_immr:
+ iounmap(priv->immr);
+out_unmap_regs:
+ iounmap(priv->regs);
+out_dma_release_channel:
+ dma_release_channel(priv->chan);
+out_carma_device_destroy:
+ carma_device_destroy(priv->devno);
+out_unregister_chrdev_region:
+ unregister_chrdev_region(priv->devno, 1);
+out_free_priv:
+ mutex_destroy(&priv->lock);
+ kfree(priv);
+out_return:
+ return ret;
+}
+
+static struct of_device_id fpga_of_match[] = {
+ { .compatible = "carma,fpga-programmer", },
+ {},
+};
+
+static struct of_platform_driver fpga_of_driver = {
+ .probe = fpga_of_probe,
+ .remove = fpga_of_remove,
+ .driver = {
+ .name = drv_name,
+ .of_match_table = fpga_of_match,
+ .owner = THIS_MODULE,
+ },
+};
+
+/*
+ * Module Init / Exit
+ */
+
+static int __init fpga_init(void)
+{
+ led_trigger_register_simple("fpga", &ledtrig_fpga);
+ return of_register_platform_driver(&fpga_of_driver);
+}
+
+static void __exit fpga_exit(void)
+{
+ of_unregister_platform_driver(&fpga_of_driver);
+ led_trigger_unregister_simple(ledtrig_fpga);
+}
+
+MODULE_AUTHOR("Ira W. Snyder <i...@ovro.caltech.edu>");
+MODULE_DESCRIPTION("CARMA Board DATA-FPGA Programmer");
+MODULE_LICENSE("GPL");
+
+module_init(fpga_init);
+module_exit(fpga_exit);
--
1.7.1
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