On Thu, May 20, 2010 at 10:49:55PM +1000, Paul Mackerras wrote: > This extends the emulate_step() function to handle most of the load > and store instructions implemented on current 64-bit server processors. > The aim is to handle all the load and store instructions used in the > kernel, so this handles the Altivec/VMX lvx and stvx and the VSX > lxv2dx and stxv2dx instructions (implemented in POWER7). >
Can the emulate_step() function be used on BookIII E processors as well (arch/powerpc/kernel/kprobes.c invokes it irrespective of the host processor though)? If yes, we can use it with hw_breakpoint_handler() of BookE processors (like what is done on the PPC64 counterpart). > The new code can emulate user mode instructions, and checks the > effective address for a load or store if the saved state is for > user mode. It doesn't handle little-endian mode at present. > > For floating-point, Altivec/VMX and VSX instructions, it checks > that the saved MSR has the enable bit for the relevant facility > set, and if so, assumes that the FP/VMX/VSX registers contain > valid state, and does loads or stores directly to/from the > FP/VMX/VSX registers, using assembly helpers in ldstfp.S. > Thanks, K.Prasad _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
