On Dec 8, 2009, at 1:31 AM, Vivek Mahajan wrote:
> Signed-off-by: Vivek Mahajan <vivek.maha...@freescale.com>
> ---
> arch/powerpc/boot/dts/p2020rdb.dts | 6 ++++++
> 1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/p2020rdb.dts
> b/arch/powerpc/boot/dts/p2020rdb.dts
> index da4cb0d..8a26050 100644
> --- a/arch/powerpc/boot/dts/p2020rdb.dts
> +++ b/arch/powerpc/boot/dts/p2020rdb.dts
> @@ -583,4 +583,10 @@
> 0x0 0x100000>;
> };
> };
> +
> + cache-s...@fff00000 {
> + fsl,cache-sram-ctlr-handle = <&L2>;
> + reg = <0 0xfff00000 0 0x10000>;
> + compatible = "fsl,p2020-cache-sram";
> + };
> };
> --
> 1.5.6.5
Sorry, we've let this sit too long:
This should be created by u-boot instead of static in the .dts. The assumption
should be the cache/SRAM is already setup this way via u-boot and its just
conveying the HW config to the kernel.
In the future we should have the kernel dynamically allocate a physical address
region for the SRAM (if its not already setup by u-boot).
- k
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