On Nov 14, 2009, at 2:42 AM, Joakim Tjernlund wrote:
..... Avoid this by always pinning
kernel instruction TLB space.
You may as well map the data space, too, since you have
reserved the entries. Take advantage of that performance.
Also, some processor variants have very few TLB entries,
and may only reserve two entries (although the flag says
reserve 4). Ensure there are sufficient resources to do
what you want. This is the reason the option is configurable.
Thanks.
-- Dan
_______________________________________________
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
