Joakim Tjernlund wrote:
Scott Wood <scottw...@freescale.com> wrote on 11/11/2009 16:26:53:
On Wed, Nov 11, 2009 at 01:06:10AM +0100, Joakim Tjernlund wrote:
Scott Wood <scottw...@freescale.com> wrote on 11/11/2009 00:21:18:
Where would you put the dcbi? How do you regain control after that
cache line has been refilled, but before code flows back to the bad branch?
The dcbi would replace the current CPU15 tlbie.
But that only works if you take an ITLB miss at the right time.
Yeah, I misread the CPU15 errata so my ideas will not work.
Anyhow, will you send a patch that make TLB pinning mandatory?
After that my series can go in.
One other concern with pinning on 8xx -- could it cause problems with
uncached DMA mappings? What happens if a speculative load pulls in a
cache line in an area that's supposed to be uncached?
-Scott
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