Joakim Tjernlund wrote:
Scott Wood <scottw...@freescale.com> wrote on 10/11/2009 00:00:04:
syscall_exit_cont, SRR0/SRR1 were being loaded immediately prior to a page
boundary, with the rfi after the page boundary. On crossing the boundary,
we take an ITLB miss (which goes from possibility to certainty with the
CPU15 workaround), and SRR0/SRR1 get clobbered.
I am not familiar with CPU15 since we never had that problem.
The patch series is OK then, but one need to add some CPU15 love?
It's not CPU15 itself that is causing the problem, but rather the
workaround for CPU15 takes something that has a possibility of happening
and makes it certain to happen.
Either that, or require that the kernel text be pinned, though that does not
interact well with CPU15.
Why does not pinning interact well with CPU15? If pinned, you never get
a TLB miss for kernel text so that should mitigate the CPU15 problem.
The nature of the workaround for CPU15 is that we can't keep it pinned
-- we have to take an ITLB miss on every page boundary crossing. If you
try to pin, it'll just be invalidated by the workaround.
There is an alternate workaround, but it requires compiler changes.
-Scott
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