> After some more thinking I don't think I do TLB Miss/Error correctly yet. > The problem is ACCESSED. Since I don't know if load or store in TLB Miss > I must choose: > - Assume load and do what you do above. That will incorrectly > set ACCESSED on store ops when mapped as RO(plus whatever more I haven't > thought about yet) > > - Trap to TLB Error and do the above. That will set ACCESSED correctly > but won't trap kernel space so these remain what they are. > Is anything depending on ACCESSED for kernel pages? > if so, what if we set ACCESSED on all kernel pages when mapping them at > boot? > Will SWAP or some other service(accounting?) not like that?
Kernel pages always have ACCESSED set and never clear it. I think the only solution here is that if -anything- doesn't look right, the TLB miss should create one of those "unpopulated" entries and we need to make sure they are properly invalidated in the subsequent fault path. I'll read the 8xx doco asap to make sure I get it right. > Finally, why do you need to include DIRTY when a store OP? > Do you need to do COW before dirtying the page? > Seems to work for me to just set DIRTY in TLB Error if RW is set too > and not trap to C. You can, but what about a load ? That shouldn't set dirty. So if you set dirty only on stores, then a load will bring in a page without dirty, you need to make sure you get another TLB error when writing to it so you get a chance to set dirty. Ben. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
