On Sep 21, 2009, at 7:30 AM, Paul Gortmaker wrote:
The PCI-e addressing was originally patterned of the MPC8548CDS which has PCI1, PCI2, and PCI-e. Since this board only has PCI1 and PCI-e, it makes more sense to be similar to the MPC8568MDS board. This does that by cutting the PCI/PCI-e I/O sizes from 16MB to 8MB and pulling the PCI-e I/O range back to 0xe280_0000 (the hole where PCI2 I/O would have been). This also fixes a typo where an extra zero made an 8MB range a 128MB range, removes the hole left by PCI2 from the aliases, and sets the clocks to match the oscillators that are actually on the board. With accompanying u-boot updates, PCI-e has been validated with both a sky2 card (1148:9e00) and an e1000 card (8086:108b). Signed-off-by: Paul Gortmaker <paul.gortma...@windriver.com> --- v2: cosmetic; fix leading zeros on 0x00800000 for better readability arch/powerpc/boot/dts/sbc8548.dts | 17 ++++++++--------- 1 files changed, 8 insertions(+), 9 deletions(-)
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