Hello Kumar Could you please accept this patch if it is okay.
Regards POonam > -----Original Message----- > From: Aggrwal Poonam-B10812 > Sent: Monday, August 31, 2009 5:22 PM > To: linuxppc-...@ozlabs.org > Cc: Aggrwal Poonam-B10812 > Subject: [PATCH][v3] powerpc/85xx: P1020RDB Support Added > > P1020 is another member of Freescale QorIQ series of processors. > It is an e500 based dual core SOC. > Being a scaled down version of P2020 it has following > differences from P2020: > - 533MHz - 800MHz core frequency. > - 256Kbyte L2 cache > - Ethernet controllers with classification capabilities(new > controller). > From board perspective P1020RDB is same as P2020RDB. > > * This code adds the basic basic platform support for P1020RDB. > > Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com> > --- > - based on > http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git > - branch->next > - The patch does not contain ethernet support because P1020 > contains new eTSEC > controller. The support will be added in the later patches. > arch/powerpc/boot/dts/p1020rdb.dts | 477 > +++++++++++++++++++++++++++++ > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 ++ > 2 files changed, 501 insertions(+), 0 deletions(-) create > mode 100644 arch/powerpc/boot/dts/p1020rdb.dts > > diff --git a/arch/powerpc/boot/dts/p1020rdb.dts > b/arch/powerpc/boot/dts/p1020rdb.dts > new file mode 100644 > index 0000000..de5672c > --- /dev/null > +++ b/arch/powerpc/boot/dts/p1020rdb.dts > @@ -0,0 +1,477 @@ > +/* > + * P1020 RDB Device Tree Source > + * > + * Copyright 2009 Freescale Semiconductor Inc. > + * > + * This program is free software; you can redistribute it and/or > +modify it > + * under the terms of the GNU General Public License as > published by > +the > + * Free Software Foundation; either version 2 of the > License, or (at > +your > + * option) any later version. > + */ > + > +/dts-v1/; > +/ { > + model = "fsl,P1020"; > + compatible = "fsl,P1020RDB"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &serial0; > + serial1 = &serial1; > + pci0 = &pci0; > + pci1 = &pci1; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + PowerPC,p1...@0 { > + device_type = "cpu"; > + reg = <0x0>; > + next-level-cache = <&L2>; > + }; > + > + PowerPC,p1...@1 { > + device_type = "cpu"; > + reg = <0x1>; > + next-level-cache = <&L2>; > + }; > + }; > + > + memory { > + device_type = "memory"; > + }; > + > + local...@ffe05000 { > + #address-cells = <2>; > + #size-cells = <1>; > + compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus"; > + reg = <0 0xffe05000 0 0x1000>; > + interrupts = <19 2>; > + interrupt-parent = <&mpic>; > + > + /* NOR and NAND Flashes */ > + ranges = <0x0 0x0 0x0 0xef000000 0x01000000 > + 0x1 0x0 0x0 0xffa00000 0x00040000 > + 0x2 0x0 0x0 0xffb00000 0x00020000>; > + > + n...@0,0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "cfi-flash"; > + reg = <0x0 0x0 0x1000000>; > + bank-width = <2>; > + device-width = <1>; > + > + partit...@0 { > + /* This location must not be altered */ > + /* 256KB for Vitesse 7385 > Switch firmware */ > + reg = <0x0 0x00040000>; > + label = "NOR (RO) Vitesse-7385 > Firmware"; > + read-only; > + }; > + > + partit...@40000 { > + /* 256KB for DTB Image */ > + reg = <0x00040000 0x00040000>; > + label = "NOR (RO) DTB Image"; > + read-only; > + }; > + > + partit...@80000 { > + /* 3.5 MB for Linux Kernel Image */ > + reg = <0x00080000 0x00380000>; > + label = "NOR (RO) Linux Kernel Image"; > + read-only; > + }; > + > + partit...@400000 { > + /* 11MB for JFFS2 based Root > file System */ > + reg = <0x00400000 0x00b00000>; > + label = "NOR (RW) JFFS2 Root > File System"; > + }; > + > + partit...@f00000 { > + /* This location must not be altered */ > + /* 512KB for u-boot Bootloader Image */ > + /* 512KB for u-boot Environment > Variables */ > + reg = <0x00f00000 0x00100000>; > + label = "NOR (RO) U-Boot Image"; > + read-only; > + }; > + }; > + > + n...@1,0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "fsl,p1020-fcm-nand", > + "fsl,elbc-fcm-nand"; > + reg = <0x1 0x0 0x40000>; > + > + partit...@0 { > + /* This location must not be altered */ > + /* 1MB for u-boot Bootloader Image */ > + reg = <0x0 0x00100000>; > + label = "NAND (RO) U-Boot Image"; > + read-only; > + }; > + > + partit...@100000 { > + /* 1MB for DTB Image */ > + reg = <0x00100000 0x00100000>; > + label = "NAND (RO) DTB Image"; > + read-only; > + }; > + > + partit...@200000 { > + /* 4MB for Linux Kernel Image */ > + reg = <0x00200000 0x00400000>; > + label = "NAND (RO) Linux Kernel Image"; > + read-only; > + }; > + > + partit...@600000 { > + /* 4MB for Compressed Root file > System Image */ > + reg = <0x00600000 0x00400000>; > + label = "NAND (RO) Compressed > RFS Image"; > + read-only; > + }; > + > + partit...@a00000 { > + /* 7MB for JFFS2 based Root > file System */ > + reg = <0x00a00000 0x00700000>; > + label = "NAND (RW) JFFS2 Root > File System"; > + }; > + > + partit...@1100000 { > + /* 15MB for JFFS2 based Root > file System */ > + reg = <0x01100000 0x00f00000>; > + label = "NAND (RW) Writable User area"; > + }; > + }; > + > + l2swi...@2,0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "vitesse-7385"; > + reg = <0x2 0x0 0x20000>; > + }; > + > + }; > + > + s...@ffe00000 { > + #address-cells = <1>; > + #size-cells = <1>; > + device_type = "soc"; > + compatible = "fsl,p1020-immr", "simple-bus"; > + ranges = <0x0 0x0 0xffe00000 0x100000>; > + bus-frequency = <0>; // Filled out by uboot. > + > + ecm-...@0 { > + compatible = "fsl,ecm-law"; > + reg = <0x0 0x1000>; > + fsl,num-laws = <12>; > + }; > + > + e...@1000 { > + compatible = "fsl,p1020-ecm", "fsl,ecm"; > + reg = <0x1000 0x1000>; > + interrupts = <16 2>; > + interrupt-parent = <&mpic>; > + }; > + > + memory-control...@2000 { > + compatible = "fsl,p1020-memory-controller"; > + reg = <0x2000 0x1000>; > + interrupt-parent = <&mpic>; > + interrupts = <16 2>; > + }; > + > + i...@3000 { > + #address-cells = <1>; > + #size-cells = <0>; > + cell-index = <0>; > + compatible = "fsl-i2c"; > + reg = <0x3000 0x100>; > + interrupts = <43 2>; > + interrupt-parent = <&mpic>; > + dfsrr; > + r...@68 { > + compatible = "dallas,ds1339"; > + reg = <0x68>; > + }; > + }; > + > + i...@3100 { > + #address-cells = <1>; > + #size-cells = <0>; > + cell-index = <1>; > + compatible = "fsl-i2c"; > + reg = <0x3100 0x100>; > + interrupts = <43 2>; > + interrupt-parent = <&mpic>; > + dfsrr; > + }; > + > + serial0: ser...@4500 { > + cell-index = <0>; > + device_type = "serial"; > + compatible = "ns16550"; > + reg = <0x4500 0x100>; > + clock-frequency = <0>; > + interrupts = <42 2>; > + interrupt-parent = <&mpic>; > + }; > + > + serial1: ser...@4600 { > + cell-index = <1>; > + device_type = "serial"; > + compatible = "ns16550"; > + reg = <0x4600 0x100>; > + clock-frequency = <0>; > + interrupts = <42 2>; > + interrupt-parent = <&mpic>; > + }; > + > + s...@7000 { > + cell-index = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,espi"; > + reg = <0x7000 0x1000>; > + interrupts = <59 0x2>; > + interrupt-parent = <&mpic>; > + mode = "cpu"; > + > + fsl_m25...@0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "fsl,espi-flash"; > + reg = <0>; > + linux,modalias = "fsl_m25p80"; > + modal = "s25sl128b"; > + spi-max-frequency = <50000000>; > + mode = <0>; > + > + partit...@0 { > + /* 512KB for u-boot > Bootloader Image */ > + reg = <0x0 0x00080000>; > + label = "SPI (RO) U-Boot Image"; > + read-only; > + }; > + > + partit...@80000 { > + /* 512KB for DTB Image */ > + reg = <0x00080000 0x00080000>; > + label = "SPI (RO) DTB Image"; > + read-only; > + }; > + > + partit...@100000 { > + /* 4MB for Linux Kernel Image */ > + reg = <0x00100000 0x00400000>; > + label = "SPI (RO) Linux > Kernel Image"; > + read-only; > + }; > + > + partit...@500000 { > + /* 4MB for Compressed > RFS Image */ > + reg = <0x00500000 0x00400000>; > + label = "SPI (RO) > Compressed RFS Image"; > + read-only; > + }; > + > + partit...@900000 { > + /* 7MB for JFFS2 based RFS */ > + reg = <0x00900000 0x00700000>; > + label = "SPI (RW) JFFS2 RFS"; > + }; > + }; > + }; > + > + gpio: gpio-control...@f000 { > + #gpio-cells = <2>; > + compatible = "fsl,mpc8572-gpio"; > + reg = <0xf000 0x100>; > + interrupts = <47 0x2>; > + interrupt-parent = <&mpic>; > + gpio-controller; > + }; > + > + L2: l2-cache-control...@20000 { > + compatible = "fsl,p1020-l2-cache-controller"; > + reg = <0x20000 0x1000>; > + cache-line-size = <32>; // 32 bytes > + cache-size = <0x40000>; // L2,256K > + interrupt-parent = <&mpic>; > + interrupts = <16 2>; > + }; > + > + d...@21300 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "fsl,eloplus-dma"; > + reg = <0x21300 0x4>; > + ranges = <0x0 0x21100 0x200>; > + cell-index = <0>; > + dma-chan...@0 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x0 0x80>; > + cell-index = <0>; > + interrupt-parent = <&mpic>; > + interrupts = <20 2>; > + }; > + dma-chan...@80 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x80 0x80>; > + cell-index = <1>; > + interrupt-parent = <&mpic>; > + interrupts = <21 2>; > + }; > + dma-chan...@100 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x100 0x80>; > + cell-index = <2>; > + interrupt-parent = <&mpic>; > + interrupts = <22 2>; > + }; > + dma-chan...@180 { > + compatible = "fsl,eloplus-dma-channel"; > + reg = <0x180 0x80>; > + cell-index = <3>; > + interrupt-parent = <&mpic>; > + interrupts = <23 2>; > + }; > + }; > + > + u...@22000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl-usb2-dr"; > + reg = <0x22000 0x1000>; > + interrupt-parent = <&mpic>; > + interrupts = <28 0x2>; > + phy_type = "ulpi"; > + }; > + > + u...@23000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl-usb2-dr"; > + reg = <0x23000 0x1000>; > + interrupt-parent = <&mpic>; > + interrupts = <46 0x2>; > + phy_type = "ulpi"; > + }; > + > + sd...@2e000 { > + compatible = "fsl,p1020-esdhc", "fsl,esdhc"; > + reg = <0x2e000 0x1000>; > + interrupts = <72 0x2>; > + interrupt-parent = <&mpic>; > + /* Filled in by U-Boot */ > + clock-frequency = <0>; > + }; > + > + cry...@30000 { > + compatible = "fsl,sec3.1", > "fsl,sec3.0", "fsl,sec2.4", > + "fsl,sec2.2", > "fsl,sec2.1", "fsl,sec2.0"; > + reg = <0x30000 0x10000>; > + interrupts = <45 2 58 2>; > + interrupt-parent = <&mpic>; > + fsl,num-channels = <4>; > + fsl,channel-fifo-len = <24>; > + fsl,exec-units-mask = <0xbfe>; > + fsl,descriptor-types-mask = <0x3ab0ebf>; > + }; > + > + mpic: p...@40000 { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + reg = <0x40000 0x40000>; > + compatible = "chrp,open-pic"; > + device_type = "open-pic"; > + }; > + > + m...@41600 { > + compatible = "fsl,p1020-msi", "fsl,mpic-msi"; > + reg = <0x41600 0x80>; > + msi-available-ranges = <0 0x100>; > + interrupts = < > + 0xe0 0 > + 0xe1 0 > + 0xe2 0 > + 0xe3 0 > + 0xe4 0 > + 0xe5 0 > + 0xe6 0 > + 0xe7 0>; > + interrupt-parent = <&mpic>; > + }; > + > + global-utilit...@e0000 { //global utilities block > + compatible = "fsl,p1020-guts"; > + reg = <0xe0000 0x1000>; > + fsl,has-rstcr; > + }; > + }; > + > + pci0: p...@ffe09000 { > + compatible = "fsl,mpc8548-pcie"; > + device_type = "pci"; > + #interrupt-cells = <1>; > + #size-cells = <2>; > + #address-cells = <3>; > + reg = <0 0xffe09000 0 0x1000>; > + bus-range = <0 255>; > + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 > 0x0 0x20000000 > + 0x1000000 0x0 0x00000000 0 0xffc30000 > 0x0 0x10000>; > + clock-frequency = <33333333>; > + interrupt-parent = <&mpic>; > + interrupts = <16 2>; > + p...@0 { > + reg = <0x0 0x0 0x0 0x0 0x0>; > + #size-cells = <2>; > + #address-cells = <3>; > + device_type = "pci"; > + ranges = <0x2000000 0x0 0xa0000000 > + 0x2000000 0x0 0xa0000000 > + 0x0 0x20000000 > + > + 0x1000000 0x0 0x0 > + 0x1000000 0x0 0x0 > + 0x0 0x100000>; > + }; > + }; > + > + pci1: p...@ffe0a000 { > + compatible = "fsl,mpc8548-pcie"; > + device_type = "pci"; > + #interrupt-cells = <1>; > + #size-cells = <2>; > + #address-cells = <3>; > + reg = <0 0xffe0a000 0 0x1000>; > + bus-range = <0 255>; > + ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 > 0x0 0x20000000 > + 0x1000000 0x0 0x00000000 0 0xffc20000 > 0x0 0x10000>; > + clock-frequency = <33333333>; > + interrupt-parent = <&mpic>; > + interrupts = <16 2>; > + p...@0 { > + reg = <0x0 0x0 0x0 0x0 0x0>; > + #size-cells = <2>; > + #address-cells = <3>; > + device_type = "pci"; > + ranges = <0x2000000 0x0 0xc0000000 > + 0x2000000 0x0 0xc0000000 > + 0x0 0x20000000 > + > + 0x1000000 0x0 0x0 > + 0x1000000 0x0 0x0 > + 0x0 0x100000>; > + }; > + }; > +}; > diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c > b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c > index c8468de..495bd8b 100644 > --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c > +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c > @@ -113,6 +113,7 @@ static int __init mpc85xxrdb_publish_devices(void) > return of_platform_bus_probe(NULL, mpc85xxrdb_ids, > NULL); } machine_device_initcall(p2020_rdb, > mpc85xxrdb_publish_devices); > +machine_device_initcall(p1020_rdb, mpc85xxrdb_publish_devices); > > /* > * Called very early, device-tree isn't unflattened @@ > -126,6 +127,15 @@ static int __init p2020_rdb_probe(void) > return 0; > } > > +static int __init p1020_rdb_probe(void) { > + unsigned long root = of_get_flat_dt_root(); > + > + if (of_flat_dt_is_compatible(root, "fsl,P1020RDB")) > + return 1; > + return 0; > +} > + > define_machine(p2020_rdb) { > .name = "P2020 RDB", > .probe = p2020_rdb_probe, > @@ -139,3 +149,17 @@ define_machine(p2020_rdb) { > .calibrate_decr = generic_calibrate_decr, > .progress = udbg_progress, > }; > + > +define_machine(p1020_rdb) { > + .name = "P1020 RDB", > + .probe = p1020_rdb_probe, > + .setup_arch = mpc85xx_rdb_setup_arch, > + .init_IRQ = mpc85xx_rdb_pic_init, > +#ifdef CONFIG_PCI > + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, > +#endif > + .get_irq = mpic_get_irq, > + .restart = fsl_rstcr_restart, > + .calibrate_decr = generic_calibrate_decr, > + .progress = udbg_progress, > +}; > -- > 1.5.6.5 > > _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
