wilbur.chan wrote:
I am using a SMP E500 v2, and I want CPU0 to write some value to a physical address, and wait for CPU1 to read from it.
Is this under Linux (it is a Linux mailing list...)? If so, there are better ways of communicating that don't involve clobbering random memory and overlapping userspace TLB mappings.
However, it seemed failed to communicate between CPUs by DRAM.. CPU1 can not read the correct value from the address where CPU1 wrote to.
Do both cores have a mapping with the M bit (memory coherence required) set? -Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
