Hi, I'm on a mpc5121 platform, kernel 2.6.24.6, and I'm using the mpc512x_psc_spi driver to communicate with a touch screen controller. I'm sending commands and reading data from the controller using 24-bit packet (3 bytes). The speed of the SPI is set to 640 KHz. I thought that I would need 8/640K = 12,5 us each byte I send, but this is not true. I'm verifying the time needed by mpc512x_psc_spi_transfer_rxtx function in order to send one byte toggling a digital output when it sets the TX/RX flags (after it copies data in the transmission buffer) and toggling the output again when the empty buffer interrupt is triggered. I see that the actual 12,5us data transfer is preceded by a 20us delay and followed by another 15,6us delay. So the transfer is done in almost 50 us.
Is this a normal behavior? Does the PSC controller need this overhead in the transfer time? DSCKI and DTL delays are set to zero. Another doubt I have: In mpc512x_psc_spi_transfer_rxtx, Mode Register 2 of the PSC is set to zero. This is done (as manual says) by access to MR1 (by a read) and then write a zero on the same address.: in_8(&psc->mode); mdelay(1); out_8(&psc->mode, 0x0); mdelay(1); I don't understand why a 1ms delay is needed. The manual doesn't say anything about this. I tried to comment out these delays and anyway it seems to work correctly. Best regards, Matteo Canella
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