On Thursday 23 April 2009, Valentine Barshak wrote: > Some U-Boot versions incorrectly set the number of chipselects to two > for Sequoia/Rainier boards while they only have one chipselect hardwired. > This patch adds a workaround for this, hardcoding the number of chipselects > to one for sequioa/rainer board models and reading the actual value from > the memory controller register DDR0_10 otherwise. > It also fixes another error in the way ibm4xx_denali_fixup_memsize > calculates memory size. When testing the DDR_REDUC bit, the polarity is > backwards. A "1" implies 32-bit wide memory while a "0" implies 64-bit > wide memory. > > Signed-off-by: Valentine Barshak <vbars...@ru.mvista.com> > Signed-off-by: Steven A. Falco <sfa...@harris.com>
Acked-by: Stefan Roese <s...@denx.de> Thanks. Best regards, Stefan _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
