On Apr 23, 2009, at 9:24 AM, Gary Thomas wrote:
I have found the culprit - in arch/powerpc/kernel/pci_32.c
static void
fixup_hide_host_resource_fsl(struct pci_dev *dev)
{
int i, class = dev->class >> 8;
#if 0
if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
class == PCI_CLASS_BRIDGE_OTHER) &&
#else
if ((class == PCI_CLASS_PROCESSOR_POWERPC) &&
#endif
(dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
(dev->bus->parent == NULL)) {
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
dev->resource[i].start = 0;
dev->resource[i].end = 0;
dev->resource[i].flags = 0;
}
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID,
fixup_hide_host_resource_fsl);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
fixup_hide_host_resource_fsl);
This function is now (the #if 0 case is in 2.6.28) tossing out
the memory resources used by the PCI bridge itself. This makes
everything fall over, at least on my 834x platform.
This change was applied 2008-10-08, but it seems incorrect on the
834x.
Its not. The PCI subsystem shouldn't be allocating or seeing the PHBs
resources.
Are you using u-boot to boot? If so is the board port public?
My systems use RedBoot (I'm the original author of RedBoot, so one
would
expect that). At this moment, the code isn't public, sorry.
Ok. Not sure if RedBoot has a simple memory dump command, but if you
can dump the IMMR registers for PCI (0x8400 - IOS and 0x8500 - PCI1).
(I'm assuming PCI1 is the one you are using). From IOS I wanted the
outbound registers, for PCI1 the inbound ATU registers.
- k
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