On Wed, Apr 01, 2009 at 08:23:42PM -0700, Sauce.Cheng wrote:
> > I don't see where you set up a BAT that covers 0xf0000000.
>
> if i have to set up a BAT that cover 0xF0000000. i had a debug with LEDs
> like that in u-boot code. everything is //normal. 0xF00000000 is the value
> of CFG_IMMR(CONFIG_SYS_IMMR) that memory map register, it is the phy address
> and //base //address of all internal regishters, isnt? you mean that if i
> set BATs, i should not get the phy address like in the //front ?
I don't quite follow the above, but what I meant is that you need to
put a mapping in place that covers your LED I/O once you have the MMU on.
Any mappings that U-boot made will be gone at that point.
> i tried
> CONFIG_PPC_EARLY_DEBUG_CPM=y
> CONFIG_PPC_EARLY_DEBUG_CPM_ADDR=0xf00000008
> how can i make sure CPM_ADDR, 0xf0000008 is default value
Look at the u-boot source, or dump the memory and see if it looks like a
ring buffer.
> PowerPC,8...@0 {
> device_type = "cpu";
> reg = <0>;
> d-cache-line-size = <d#32>;
> i-cache-line-size = <d#32>;
> d-cache-size = <d#16384>;
> i-cache-size = <d#16384>;
This is a dts-v0 tree, which implies it's fairly old.
> b...@119f0 {
> compatible = "fsl,mpc8272-brg",
> "fsl,cpm2-brg",
> "fsl,cpm-brg";
> reg = <119f0 10 115f0 10>;
> };
Make sure that the clock-frequency property of the brg node is being set
by u-boot. I should probably send a patch for that while the merge
window's still open...
> ser...@11a82 {
> device_type = "serial";
> compatible = "fsl,mpc8272-smc-uart",
> "fsl,cpm2-smc-uart";
> reg = <11a82 20 87FC 100>;
regs = <11a80 20 87fc 2>;
> interrupts = <28 8>;
interrupts = <4 8>;
> interrupt-parent = <&PIC>;
> fsl,cpm-brg = <1>;
> fsl,cpm-command = <00800000>;
You need to update fsl,cpm-command; that is the SCC1 command word.
The SMC1 command is 0x1d000000 (see the ep8248e device tree).
Also make sure that the brg is correct.
-Scott
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