On Fri, 6 Feb 2009 21:07:01 +0300 Anton Vorontsov <avoront...@ru.mvista.com> wrote:
> This patch adds SDHCI_QUIRK_FSL quirk. The quirk is used to instruct
> the sdhci driver about various FSL eSDHC host incompatibilities:
>
No device quirks please. They should be for specific bugs, not lumping
things together like this. Otherwise we'll soon have an unmanageable
mess.
> 1) FSL eSDHC controllers can support maximum block size up to 4096
> bytes. The MBL (Maximum Block Length) field in the capabilities
> register extended by one bit.
>
> (Should we implement a dedicated quirk for this? I.e.
> SDHCI_QUIRK_MAX_BLK_SZ_4096?)
>
Yes please. It would have to mean "always support 4096" though, not
"turn reserved bit 18 into a block length bit".
> 2) sdhci_init() is needed after error conditions.
>
> (Can we safely do this for all controllers?)
>
Please investigate which part of sdhci_init() is needed. How does it
break without this?
> 3) Small udelay is needed to make eSDHC work in PIO mode. Without
> the delay reading causes endless interrupt storm, and writing
> corrupts data. The first guess would be that we must wait for
> some bit in some register, but I didn't find any reliable bits
> that changes before and after the delay. Though, more investigation
> on this is in my todo list.
Please try to investigate more, but if you cannot improve it further
then a specific quirk can be added.
Rgds
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-- Pierre Ossman
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