This series of patches is aimed at supporting SMP on non-hash based processors. It consists of a rework of the MMU context management and TLB management, clearly splitting hash32, hash64 and nohash in both cases, adding SMP safe context handling and some basic SMP TLB management.
There is room for improvements, such as implementing lazy TLB flushing on processors without invalidate-by-PID support HW, some better IPI mechanism, support for variable sizes PID, lock less fast path in the MMU context switch, etc... but it should basically work. There are some semingly unrelated patches in the pile as they are dependencies of the main ones so I'm including them in. Some of these may already have been applied in Kumar or jwb tree. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev