On Thu, 2008-12-04 at 07:33 -0500, Josh Boyer wrote: > On Thu, 04 Dec 2008 17:12:59 +1100 > Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote: > > > We were missing the CPU_FTR_NOEXECUTE bit in our cputable for all > > these processors. The result is that update_mmu_cache() would flush > > the cache for all pages mapped to userspace which is totally > > unnecessary on those processors since we already handle flushing > > on execute in the page fault path. > > > > This should provide a nice speed up ;-) > > Did you test it this time? If so, how and what were the results?
Yes, I verified I no longer had PG_arch1 all over my PCI GART pages with DRI enabled :-) I didn't actually benchmark anything. Cheers, Ben. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
