On Mon, 2008-12-01 at 15:28 -0800, Mike Ditto wrote:
> Laurent Pinchart <[EMAIL PROTECTED]> wrote:
> > Transmission timeout after one second. The first TX buffer descriptor
> > status
> > hasn't been modified by the CPM. The CPM state dump shows that processing
> > of
> ...
>
> This sounds very similar to a problem I have seen on MPC8247 and
> MPC8248.
>
> It could be a variation of the CPM bug documented by Freescale as
> erratum CPM98. But the key difference is that we see a persistent
> failure, while the erratum only mentions a problem with "the next
> transaction". What we see is that once the I2C engine gets confused
> by some anomaly on the SCL signal, it stops processing buffer
> descriptors entirely until it is turned off and back on. You can
> observe this bug by momentarily grounding the SCL line (it's an
> open-collector bus) with a jumper while you attempt an I/O.
>
> Our production equipment is using Linux 2.6 with the out-of-tree
> i2c-algo-8260.c by Dan Malek and Brad Parker. I modified this
> driver to shut off the I2C controller and turn it back on when it
> hits this problem, and now it can recover from this condition.
>
> However, this does not explain how the controller gets into the
> frozen state in the first place. We see it very rarely in production
> units and have not been able to identify the cause. If it is
> similar to erratum CPM98 then it could be noise on the SCL signal or
> perhaps an I2C device that doesn't conform to the protocol perfectly.
> Also beware, if you are using some kind of multiplexer, that you don't
> direct the multiplexer to switch to a different bus (segment) while a
> transaction is in progress.
>
> In testing with the current (2.6.27) i2c-cpm.c driver, I found that
> it is sufficient to #define I2C_CHIP_ERRATA to allow it to recover
> from the CPM I2C freeze. However, I don't know if I like this
> approach because it turns off the I2C engine after every transfer,
> even successful ones, and I don't know if this will affect reliability
> or performance. And I don't know if this will actually prevent the
> freeze from happening, although I presume that it would protect the
> I2C engine from getting confused by a glitch that happens while no
> transfer is in progress.
>
> I am not aware of any documentation for what exactly the I2C_CHIP_ERRATA
> conditional code in i2c-cpm.c is meant to work around.
The I2C_CHIP_ERRATA is mine and refers to mpc8xx, mpc860 in my case. The
driver was adapted by me some years ago in 2.4 and now someone has
ported it to 2.6 it seems. From memory, you should check that mrblr is
one byte bigger than your max transfer size.
I have include my old driver that we still use in 2.4, as I recall, not
all bits made into the kernel.
Jocke
/*
* i2c-algo-8xx.c i2x driver algorithms for MPC8XX CPM
* Copyright (c) 1999 Dan Malek ([EMAIL PROTECTED]).
*
* moved into proper i2c interface; separated out platform specific
* parts into ic-rpx.c
* Brad Parker ([EMAIL PROTECTED])
*/
/* $Id: i2c-algo-8xx.c,v 1.3 2001/11/21 17:20:22 jocke Exp $ */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/version.h>
#include <linux/init.h>
#include <asm/uaccess.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <asm/mpc8xx.h>
#include <asm/commproc.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-8xx.h>
#define CPM_MAX_READ 513
/* #define I2C_CHIP_ERRATA */ /* Try uncomment this if you have an older CPU(earlier than rev D4) */
static wait_queue_head_t iic_wait;
static ushort r_tbase, r_rbase;
static int cpm_scan = 0;
static int cpm_debug = 0;
static void
cpm_iic_interrupt(void *dev_id, struct pt_regs *regs)
{
volatile i2c8xx_t *i2c = (i2c8xx_t *)dev_id;
if (cpm_debug > 1)
printk("cpm_iic_interrupt(dev_id=%p)\n", dev_id);
#if 0
/* Chip errata, clear enable. This is not needed on rev D4 CPUs */
/* This should probably be removed and replaced by I2C_CHIP_ERRATA stuff */
/* Someone with a buggy CPU needs to confirm that */
i2c->i2c_i2mod &= ~1;
#endif
/* Clear interrupt.
*/
i2c->i2c_i2cmr = 0;
/* Get 'me going again.
*/
#ifdef INTERRUPTIBLE
wake_up_interruptible(&iic_wait);
#else
wake_up(&iic_wait);
#endif
}
static void
cpm_iic_init(struct i2c_algo_8xx_data *cpm_adap)
{
volatile iic_t *iip = cpm_adap->iip;
volatile i2c8xx_t *i2c = cpm_adap->i2c;
unsigned char brg;
bd_t *bd = (bd_t *)__res;
if (cpm_debug) printk("cpm_iic_init()\n");
/* Initialize the parameter ram.
* We need to make sure many things are initialized to zero,
* especially in the case of a microcode patch.
*/
iip->iic_rstate = 0;
iip->iic_rdp = 0;
iip->iic_rbptr = 0;
iip->iic_rbc = 0;
iip->iic_rxtmp = 0;
iip->iic_tstate = 0;
iip->iic_tdp = 0;
iip->iic_tbptr = 0;
iip->iic_tbc = 0;
iip->iic_txtmp = 0;
/* Set up the IIC parameters in the parameter ram.
*/
iip->iic_tbase = r_tbase = cpm_adap->dp_addr;
iip->iic_rbase = r_rbase = cpm_adap->dp_addr + sizeof(cbd_t)*2;
iip->iic_tfcr = SMC_EB;
iip->iic_rfcr = SMC_EB;
/* Set maximum receive size.
*/
iip->iic_mrblr = CPM_MAX_READ;
/* Initialize Tx/Rx parameters.
*/
if (cpm_adap->reloc == 0) {
volatile cpm8xx_t *cp = cpm_adap->cp;
cp->cp_cpcr =
mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
while (cp->cp_cpcr & CPM_CR_FLG);
} else {
iip->iic_rbptr = iip->iic_rbase;
iip->iic_tbptr = iip->iic_tbase;
iip->iic_rstate = 0;
iip->iic_tstate = 0;
}
/* Select an arbitrary address. Just make sure it is unique.
*/
i2c->i2c_i2add = 0xfe;
/* Make clock run at 80 KHz.
*/
brg = (unsigned char) (bd->bi_intfreq/(32*2*80000) -3);
i2c->i2c_i2brg = brg;
i2c->i2c_i2mod = 0x00;
i2c->i2c_i2com = 0x01; /* Master mode */
/* Disable interrupts.
*/
i2c->i2c_i2cmr = 0;
i2c->i2c_i2cer = 0xff;
init_waitqueue_head(&iic_wait);
/* Install interrupt handler.
*/
cpm_install_handler(CPMVEC_I2C, cpm_iic_interrupt, (void *)i2c);
}
static int
cpm_iic_shutdown(struct i2c_algo_8xx_data *cpm_adap)
{
volatile i2c8xx_t *i2c = cpm_adap->i2c;
/* Shut down IIC.
*/
i2c->i2c_i2mod &= ~1;
i2c->i2c_i2cmr = 0;
i2c->i2c_i2cer = 0xff;
return(0);
}
#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */
#define BD_SC_OV ((ushort)0x0002) /* OV - receive overrun */
#define CPM_CR_CLOSE_RXBD ((ushort)0x0007)
static void force_close(struct i2c_algo_8xx_data *cpm)
{
volatile i2c8xx_t *i2c = cpm->i2c;
if (cpm->reloc == 0) { /* micro code disabled */
volatile cpm8xx_t *cp = cpm->cp;
if (cpm_debug) printk("force_close()\n");
cp->cp_cpcr =
mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_CLOSE_RXBD) |
CPM_CR_FLG;
while (cp->cp_cpcr & CPM_CR_FLG);
}
i2c->i2c_i2cmr = 0x00; /* Disable all interrupts */
i2c->i2c_i2cer = 0xff;
}
#define __wait_event_interruptible_tmo(wq, condition, ret) \
do { \
wait_queue_t __wait; \
init_waitqueue_entry(&__wait, current); \
\
add_wait_queue(&wq, &__wait); \
for (;;) { \
set_current_state(TASK_INTERRUPTIBLE); \
if (condition) \
break; \
if (!signal_pending(current)) { \
ret = schedule_timeout(ret); \
if (!ret) \
break; \
continue; \
} \
ret = -ERESTARTSYS; \
break; \
} \
current->state = TASK_RUNNING; \
remove_wait_queue(&wq, &__wait); \
} while (0)
#define wait_event_interruptible_tmo(wq, condition, tmo) \
({ \
long __ret = tmo; \
if (!(condition)) \
__wait_event_interruptible_tmo(wq, condition, __ret); \
__ret; \
})
void
cpm_reset_i2c(volatile iic_t *iip, volatile i2c8xx_t *i2c)
{
// Disable interrupts.
i2c->i2c_i2cmr = 0;
i2c->i2c_i2cer = 0xff;
// Clear enable
i2c->i2c_i2mod &= ~1;
// Reset internal state
iip->iic_rstate = 0;
iip->iic_tstate = 0;
iip->iic_rbptr = iip->iic_rbase;
iip->iic_tbptr = iip->iic_tbase;
}
/* Read from IIC...
* abyte = address byte, with r/w flag already set
*/
static int
cpm_iic_read(struct i2c_algo_8xx_data *cpm, u_char abyte, char *buf, int count)
{
volatile iic_t *iip = cpm->iip;
volatile i2c8xx_t *i2c = cpm->i2c;
volatile cpm8xx_t *cp = cpm->cp;
volatile cbd_t *tbdf, *rbdf;
long tmo;
if (count >= CPM_MAX_READ)
return -EINVAL;
tbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_tbase];
rbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_rbase];
/* To read, we need an empty buffer of the proper length.
* All that is used is the first byte for address, the remainder
* is just used for timing (and doesn't really have to exist).
*/
clean_dcache_range((unsigned long)&abyte, (unsigned long)(&abyte+1));
if (cpm_debug) printk("cpm_iic_read(abyte=0x%x)\n", abyte);
tbdf->cbd_bufaddr = __pa(&abyte); /* Device address byte w/rw flag */
tbdf->cbd_datlen = count + 1;
tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST |
BD_SC_WRAP | BD_IIC_START;
iip->iic_mrblr = count +1; /* prevent excessive read, +1
is needed otherwise will the
RXB interrupt come too early */
/* flush will invalidate too. */
flush_dcache_range((unsigned long)buf, (unsigned long)(buf+count));
rbdf->cbd_datlen = 0;
rbdf->cbd_bufaddr = __pa(buf);
rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP| BD_SC_INTRPT;
/* Chip bug, set enable here */
i2c->i2c_i2cer = 0xff; /* Clear all pending interrupts */
i2c->i2c_i2cmr = 0x15; /* Enable some interrupts */
i2c->i2c_i2mod |= 1; /* Enable */
i2c->i2c_i2com |= 0x80 | 0x01; /* Begin transmission and force master.
* Some errors(CL) clears the M/S bit */
/* Wait for IIC transfer */
#ifdef INTERRUPTIBLE
tmo = wait_event_interruptible_tmo(iic_wait, i2c->i2c_i2cer, HZ);
#else
tmo = sleep_on_timeout(&iic_wait,1*HZ);
#endif
#ifdef I2C_CHIP_ERRATA
/* Chip errata, clear enable. This is not needed on rev D4 CPUs.
Disabling I2C too early may cause too short stop condition */
udelay(4);
i2c->i2c_i2mod &= ~1;
#endif
#ifdef INTERRUPTIBLE
if (signal_pending(current)){
force_close(cpm);
return -EIO;
}
#endif
if (!tmo) {
if (cpm_debug)
printk("IIC read: timeout\n");
cpm_reset_i2c(iip, i2c);
//return -ETIMEDOUT; /* timeout */
return -EREMOTEIO;
}
if (tbdf->cbd_sc & (BD_SC_READY | BD_SC_NAK | BD_SC_UN | BD_SC_CL)) {
if (cpm_debug && tbdf->cbd_sc & BD_SC_READY)
printk("IIC read; complete but tbuf ready\n");
if (cpm_debug && tbdf->cbd_sc & BD_SC_NAK)
printk("IIC read; no ack\n");
if (cpm_debug && tbdf->cbd_sc & BD_SC_UN)
printk("IIC read; TX underrun\n");
if (cpm_debug && tbdf->cbd_sc & BD_SC_CL)
printk("IIC read; TX collision\n");
cpm_reset_i2c(iip, i2c);
return -EREMOTEIO;
}
if (rbdf->cbd_sc & (BD_SC_EMPTY | BD_SC_OV)) {
if (cpm_debug && rbdf->cbd_sc & BD_SC_EMPTY)
printk("IIC read; complete but rbuf empty\n");
if (cpm_debug && rbdf->cbd_sc & BD_SC_OV)
printk("IIC read; Overrun\n");
cpm_reset_i2c(iip, i2c);
return -EREMOTEIO;
}
if (rbdf->cbd_datlen < count) {
if (cpm_debug)
printk("IIC read; short, wanted %d got %d\n",
count, rbdf->cbd_datlen);
cpm_reset_i2c(iip, i2c);
return -EREMOTEIO;
}
return count;
}
/* Write to IIC...
* addr = address byte, with r/w flag already set
*/
static int
cpm_iic_write(struct i2c_algo_8xx_data *cpm, u_char abyte, char *buf,int count)
{
volatile iic_t *iip = cpm->iip;
volatile i2c8xx_t *i2c = cpm->i2c;
volatile cpm8xx_t *cp = cpm->cp;
volatile cbd_t *tbdf;
long tmo;
clean_dcache_range((unsigned long)&abyte, (unsigned long)(&abyte+1));
flush_dcache_range((unsigned long)buf, (unsigned long)(buf+count));
if (cpm_debug) printk("cpm_iic_write(abyte=0x%x)\n", abyte);
/* set up 2 descriptors */
tbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_tbase];
tbdf[0].cbd_bufaddr = __pa(&abyte);
tbdf[0].cbd_datlen = 1;
tbdf[0].cbd_sc = BD_SC_READY | BD_IIC_START;
tbdf[1].cbd_bufaddr = __pa(buf);
tbdf[1].cbd_datlen = count;
tbdf[1].cbd_sc = BD_SC_READY | BD_SC_INTRPT | BD_SC_LAST | BD_SC_WRAP;
i2c->i2c_i2cer = 0xff;
i2c->i2c_i2cmr = 0x16; /* Enable some interupts */
/* Chip bug, set enable here */
i2c->i2c_i2mod |= 1; /* Enable */
i2c->i2c_i2com |= 0x80 | 0x01; /* Begin transmission and force master.
* Some errors(CL) clears the M/S bit */
/* Wait for IIC transfer */
#ifdef INTERRUPTIBLE
tmo = wait_event_interruptible_tmo(iic_wait, i2c->i2c_i2cer, HZ);
#else
tmo = sleep_on_timeout(&iic_wait,1*HZ);
#endif
#if I2C_CHIP_ERRATA
/* Chip errata, clear enable. This is not needed on rev D4 CPUs.
Disabling I2C too early may cause too short stop condition */
udelay(4);
i2c->i2c_i2mod &= ~1;
#endif
#ifdef INTERRUPTIBLE
if (signal_pending(current)){
force_close(cpm);
return -EIO;
}
#endif
if (!tmo) {
if (cpm_debug)
printk("IIC write: timeout\n");
cpm_reset_i2c(iip, i2c);
//return -ETIMEDOUT; /* timeout */
return -EREMOTEIO;
}
if (tbdf->cbd_sc & (BD_SC_READY | BD_SC_NAK | BD_SC_UN | BD_SC_CL)) {
if (cpm_debug && tbdf->cbd_sc & BD_SC_READY)
printk("IIC write; complete but tbuf ready\n");
if (cpm_debug && tbdf->cbd_sc & BD_SC_NAK)
printk("IIC write; no ack\n");
if (cpm_debug && tbdf->cbd_sc & BD_SC_UN)
printk("IIC write; TX underrun\n");
if (cpm_debug && tbdf->cbd_sc & BD_SC_CL)
printk("IIC write; TX collision\n");
cpm_reset_i2c(iip, i2c);
return -EREMOTEIO;
}
if (tbdf[1].cbd_sc & (BD_SC_READY | BD_SC_NAK | BD_SC_UN | BD_SC_CL)) {
if (cpm_debug && tbdf[1].cbd_sc & BD_SC_READY)
printk("IIC write2; complete but tbuf ready\n");
if (cpm_debug && tbdf[1].cbd_sc & BD_SC_NAK)
printk("IIC write2; no ack\n");
if (cpm_debug && tbdf->cbd_sc & BD_SC_UN)
printk("IIC write2; TX underrun\n");
if (cpm_debug && tbdf->cbd_sc & BD_SC_CL)
printk("IIC write2; TX collision\n");
cpm_reset_i2c(iip, i2c);
return -EREMOTEIO;
}
return count;
}
/* See if an IIC address exists..
* addr = 7 bit address, unshifted
*/
static int
cpm_iic_tryaddress(struct i2c_algo_8xx_data *cpm, int addr)
{
volatile iic_t *iip = cpm->iip;
volatile i2c8xx_t *i2c = cpm->i2c;
volatile cpm8xx_t *cp = cpm->cp;
volatile cbd_t *tbdf, *rbdf;
u_char *tb;
unsigned long len;
if (cpm_debug > 1)
printk("cpm_iic_tryaddress(cpm=%p,addr=%d)\n", cpm, addr);
if (cpm_debug && addr == 0) {
printk("iip %p, dp_addr 0x%x\n", cpm->iip, cpm->dp_addr);
printk("iic_tbase %d, r_tbase %d\n", iip->iic_tbase, r_tbase);
}
tbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_tbase];
rbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_rbase];
tb = cpm->temp;
/* do a simple read */
tb[0] = (addr << 1) | 1; /* device address (+ read) */
len = 2;
flush_dcache_range((unsigned long)tb, (unsigned long)(tb+2));
tbdf->cbd_bufaddr = __pa(tb);
tbdf->cbd_datlen = len;
tbdf->cbd_sc =
BD_SC_READY | BD_SC_LAST |
BD_SC_WRAP | BD_IIC_START;
rbdf->cbd_datlen = 0;
rbdf->cbd_bufaddr = __pa(tb+1);
rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP | BD_SC_INTRPT;
i2c->i2c_i2cmr = 0x0; /* Disable all interupts */
i2c->i2c_i2cer = 0xff;
i2c->i2c_i2mod |= 1; /* Enable */
i2c->i2c_i2com |= 0x80; /* Begin transmission */
if (cpm_debug > 1) printk("about to sleep\n");
/* wait for IIC transfer */
while(!i2c->i2c_i2cer); /* Busy wait*/
#ifdef I2C_CHIP_ERRATA
/* Chip errata, clear enable. This is not needed on rev D4 CPUs.
Disabling I2C too early may cause too short stop condition */
udelay(4);
i2c->i2c_i2mod &= ~1;
#endif
if (signal_pending(current)){
force_close(cpm);
return -EIO;
}
if (cpm_debug > 1) printk("back from sleep\n");
if (tbdf->cbd_sc & BD_SC_NAK) {
if (cpm_debug > 1) printk("IIC try; no ack\n");
return 0;
}
if (tbdf->cbd_sc & BD_SC_READY) {
printk("IIC try; complete but tbuf ready\n");
}
return 1;
}
static int cpm_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg msgs[],
int num)
{
struct i2c_algo_8xx_data *adap = i2c_adap->algo_data;
struct i2c_msg *pmsg;
int i, ret;
u_char addr;
bd_t *bd = (bd_t *)__res;
for (i = 0; i < num; i++) {
pmsg = &msgs[i];
if (cpm_debug)
printk("cmp_xfer: "
"#%d addr=0x%x flags=0x%x len=%d\n buf=%lx\n",
i, pmsg->addr, pmsg->flags, pmsg->len, (unsigned long)pmsg->buf);
if (bd->board_type == CU_BOARDTYPE || bd->board_type == CU2_BOARDTYPE) {
if (pmsg->addr & 0x8000)
cpmp->cp_pbdat |= 0x00000002;
else
cpmp->cp_pbdat &= ~0x00000002;
} else {
cpmp->cp_pbdat &= ~0x00000600; /* set to low */
if (pmsg->addr & 0x8000)
cpmp->cp_pbdat |= 0x00000400;
if (pmsg->addr & 0x4000)
cpmp->cp_pbdat |= 0x00000200;
}
addr = (pmsg->addr & ~0xc000) << 1;
if (pmsg->flags & I2C_M_RD )
addr |= 1;
if (pmsg->flags & I2C_M_REV_DIR_ADDR )
addr ^= 1;
if (!(pmsg->flags & I2C_M_NOSTART)) {
}
if (pmsg->flags & I2C_M_RD ) {
/* read bytes into buffer*/
ret = cpm_iic_read(adap, addr, pmsg->buf, pmsg->len);
if (cpm_debug)
printk("i2c-algo-8xx.o: read %d bytes\n", ret);
if (ret < pmsg->len ) {
return (ret<0)? ret : -EREMOTEIO;
}
} else {
/* write bytes from buffer */
ret = cpm_iic_write(adap, addr, pmsg->buf, pmsg->len);
if (cpm_debug)
printk("i2c-algo-8xx.o: wrote %d\n", ret);
if (ret < pmsg->len ) {
return (ret<0) ? ret : -EREMOTEIO;
}
}
}
return (num);
}
#define I2C_BITRATE 0x070f
static int algo_control(struct i2c_adapter *adapter,
unsigned int cmd, unsigned long arg)
{
struct i2c_algo_8xx_data *adap = adapter->algo_data;
volatile i2c8xx_t *i2c = adap->i2c;
unsigned char brg;
bd_t *bd = (bd_t *)__res;
switch(cmd){
case I2C_BITRATE:
brg = (unsigned char) (bd->bi_intfreq/(32*2*arg) -3);
printk("IntFreq: %lu I2C brg: %lu\n", bd->bi_intfreq, (unsigned long)brg);
i2c->i2c_i2brg = brg;
return 0;
break;
default:
return -EINVAL;
}
}
static u32 cpm_func(struct i2c_adapter *adap)
{
return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
I2C_FUNC_PROTOCOL_MANGLING;
}
/* -----exported algorithm data: ------------------------------------- */
static struct i2c_algorithm cpm_algo = {
"MPX8XX CPM algorithm",
I2C_ALGO_MPC8XX,
cpm_xfer,
NULL,
NULL, /* slave_xmit */
NULL, /* slave_recv */
algo_control, /* ioctl */
cpm_func, /* functionality */
};
/*
* registering functions to load algorithms at runtime
*/
int i2c_8xx_add_bus(struct i2c_adapter *adap)
{
int i;
struct i2c_algo_8xx_data *cpm_adap = adap->algo_data;
if (cpm_debug)
printk("i2c-algo-8xx.o: hw routines for %s registered.\n",
adap->name);
/* register new adapter to i2c module... */
adap->id |= cpm_algo.id;
adap->algo = &cpm_algo;
#ifdef MODULE
MOD_INC_USE_COUNT;
#endif
i2c_add_adapter(adap);
cpm_iic_init(cpm_adap);
/* scan bus */
if (cpm_scan) {
printk(KERN_INFO " i2c-algo-8xx.o: scanning bus %s...\n",
adap->name);
for (i = 0; i < 128; i++) {
if (cpm_iic_tryaddress(cpm_adap, i)) {
printk("(%02x)",i<<1);
}
}
printk("\n");
}
return 0;
}
int i2c_8xx_del_bus(struct i2c_adapter *adap)
{
int res;
struct i2c_algo_8xx_data *cpm_adap = adap->algo_data;
cpm_iic_shutdown(cpm_adap);
if ((res = i2c_del_adapter(adap)) < 0)
return res;
printk("i2c-algo-8xx.o: adapter unregistered: %s\n",adap->name);
#ifdef MODULE
MOD_DEC_USE_COUNT;
#endif
return 0;
}
EXPORT_SYMBOL(i2c_8xx_add_bus);
EXPORT_SYMBOL(i2c_8xx_del_bus);
int __init i2c_algo_8xx_init (void)
{
printk("i2c-algo-8xx.o: i2c mpc8xx algorithm module\n");
return 0;
}
#ifdef MODULE
MODULE_AUTHOR("Brad Parker <[EMAIL PROTECTED]>");
MODULE_DESCRIPTION("I2C-Bus MPC8XX algorithm");
int init_module(void)
{
return i2c_algo_8xx_init();
}
void cleanup_module(void)
{
}
#endif
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