On Mon, 24 Nov 2008, Morrison, Tom wrote: > Running 2.6.23.25 kernel... > > I have an external watchdog timer that is going off - and pulsing into > the MCP0 of the 8572E. I get the printk indicating that the MCP0 went > off - the problem is - how do I clear the condition that caused this > because my hardware engineer swears that the pulse is ONLY 250ms - and > after resetting several status registers (mcpsumr & rst > (because my hardware engineer swears that the pulse is ONLY 250ms long > (and I have a delay after my printk of 250ms)) - so I am pretty sure > > I am resetting the conditions mcpsumr (also, extra: the rstsr), > but after writing mcpsumr - and reading back - it still has > the mcp0 bit set? > > Where else do I need to reset the status - I think I am doing it > right... > but it isn't clearing the exception - and it 'dies' the next time > through > this (why is another problem - but first, I'd like to know why the > condition > is NOT being cleared...at all)...
SRESET# also sets MCP0 and MCP1, maybe that is on? I'd also check the EMCP bit in SPRN_HID0 (on core 0 for MCP0). _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
