Patches 1-3 fix the MPC7450 perf driver's event tables against the manual (MPC7450UM Rev. 5, chapter 11). The worst is patch 3: an alternatives row joins three different events, so perf can report the count of a different event. In one test it was 374 times the real count.
Patch 4 fills in the L1 data cache events, patch 5 adds the PMC6 copies of five L3 events to the alternatives table, and patch 6 adds a format/ directory. Patch 7 takes sample addresses from SIAR on 32-bit. When a counter overflows with interrupts disabled, the interrupted PC is where they are re-enabled; SIAR is not. Patch 8 names the events in sysfs. Tested on an iMac G4 (MPC7448). The 7448 has no L3, so patch 5 and the L3 half of patch 8 are untested. Signed-off-by: Matt Turner <[email protected]> --- Matt Turner (8): powerpc/perf: mpc7450: Event 0x30d does not use the threshold powerpc/perf: mpc7450: Event 0x634 counts L2 prefetches, not L1I powerpc/perf: mpc7450: Remove the snoop retry alternatives powerpc/perf: mpc7450: Fill in the L1 data cache events powerpc/perf: mpc7450: Add the PMC6 L3 events to the alternatives table powerpc/perf: mpc7450: Export the event format in sysfs powerpc/perf: Use SIAR for sample addresses on 32-bit powerpc/perf: mpc7450: Export event names in sysfs arch/powerpc/perf/core-book3s.c | 55 ++++--- arch/powerpc/perf/mpc7450-events-list.h | 250 ++++++++++++++++++++++++++++++++ arch/powerpc/perf/mpc7450-pmu.c | 118 +++++++++++++-- 3 files changed, 388 insertions(+), 35 deletions(-) --- base-commit: d68ce4e71248e1ff5af9654b407541d9260b3ba5 change-id: 20261106-ppc32-perf-bfa132a142db Best regards, -- Matt Turner <[email protected]>
