This series modernizes the QUICC Engine Port Interrupt Controller (QE
PIC) driver and adds the ability for QE GPIO pins to generate interrupts
through the QE PIC, completing Christophe Leroy's prior work [1].
Christophe's series was partially merged; patches 4, 6 and 7 did not
make it to mainline.
The series is organized in three parts:
1) Add missing chained_irq_{enter,exit}() calls
- In a chained handler, the parent controller need to mask and ack
the interrupt source.
2) DT binding updates
- Update #interrupt-cells from 1 to 2 in the QE PIC binding so
consumers can encode the interrupt type (falling-edge or
both-edges).
- Convert the QE GPIO binding from freeform text to DT schema.
- Extend the QE GPIO binding with an interrupt-map (nexus node) that
maps GPIO lines to parent QE PIC interrupts. This approach was
suggested by Rob Herring [2] as an alternative to using compatible
strings and driver data to specify which pins support interrupts in
a given bank.
3) QE PIC driver refactoring
- The QE PIC is a perfect fit to use the generic irq framework
instead. Perform the necessary changes to the driver to convert it.
- Minor cleanups.
4) QE GPIO interrupt support
- Add a to_irq() method to the QE GPIO driver that perform the
mapping of the GPIO pin to the parent interrupt domain, allowing
GPIO pins to be used as interrupt sources through the QE PIC via
gpio_to_irq().
[1]
https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/[email protected]/
Signed-off-by: Paul Louvel <[email protected]>
---
Christophe Leroy (1):
dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema
Paul Louvel (11):
soc: fsl: qe: Add chained_irq_{enter,exit}() calls in cascade handler
dt-bindings: soc: fsl: qe: Set #interrupt-cells to 2 to support interrupt
type encoding
dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO
soc: fsl: qe: Use generic_handle_domain_irq()
soc: fsl: qe: Iterate over all pending interrupts in cascade handler
soc: fsl: qe: Handle spurious interrupts
soc: fsl: qe: Convert to generic IRQ chip
soc: fsl: qe: Rename irq variable to parent_irq
soc: fsl: qe: Rename host member to domain in struct qepic_data
soc: fsl: qe: Remove useless struct member
soc: fsl: qe: Add support of IRQs in QE GPIO
.../bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml | 108 ++++++++++++++++
.../interrupt-controller/fsl,qe-ports-ic.yaml | 4 +-
.../bindings/soc/fsl/cpm_qe/qe/par_io.txt | 26 +---
arch/powerpc/platforms/Kconfig | 1 +
drivers/soc/fsl/qe/gpio.c | 28 +++-
drivers/soc/fsl/qe/qe_ports_ic.c | 144 +++++++++++++--------
6 files changed, 232 insertions(+), 79 deletions(-)
---
base-commit: f1b7f9c6e1a7fc549f37cafb48d233c9f7c26adc
change-id: 20260513-qe-pic-gpios-073e284615a3
Best regards,
--
Paul Louvel, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
