[PATCH v2] powerpc: FPGA support for GE Fanuc SBC610

[Martyn Welch]

Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC
MPC8641D).

This patch adds support for the registers held in the devices main FPGA,
exposing extra information about the revision of the board through cpuinfo.

Signed-off-by: Martyn Welch <[EMAIL PROTECTED]>
---

Kumar: Sorry for the delay, I was on holiday.

This patch has been reworked to apply on top of Becky's show_cpuinfo patch
(0161dca52d950676d727336cef1441ea2bcfba98)

 arch/powerpc/boot/dts/gef_sbc610.dts     |    4 +++
 arch/powerpc/platforms/86xx/gef_sbc610.c |   39 ++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts 
b/arch/powerpc/boot/dts/gef_sbc610.dts
index 771a776..6ed6083 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -84,6 +84,10 @@
                          6 0 0xfd000000 0x00800000     // IO FPGA (8-bit)
                          7 0 0xfd800000 0x00800000>;   // IO FPGA (32-bit)
 
+               [EMAIL PROTECTED],0 {
+                       compatible = "gef,fpga-regs";
+                       reg = <0x4 0x0 0x40>;
+               };
                gef_pic: [EMAIL PROTECTED],4000 {
                        #interrupt-cells = <1>;
                        interrupt-controller;
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c 
b/arch/powerpc/platforms/86xx/gef_sbc610.c
index 3873c20..64162b6 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -73,6 +73,7 @@ static void __init gef_sbc610_init_irq(void)
 
 static void __init gef_sbc610_setup_arch(void)
 {
+       struct device_node *regs;
 #ifdef CONFIG_PCI
        struct device_node *np;
 
@@ -86,8 +87,42 @@ static void __init gef_sbc610_setup_arch(void)
 #ifdef CONFIG_SMP
        mpc86xx_smp_init();
 #endif
+
+       /* Remap basic board registers */
+       regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
+       if (regs) {
+               sbc610_regs = of_iomap(regs, 0);
+               if (sbc610_regs == NULL)
+                       printk(KERN_WARNING "Unable to map board registers\n");
+       }
+}
+
+/* Return the PCB revision */
+static unsigned int gef_sbc610_get_pcb_rev(void)
+{
+       unsigned int reg;
+
+       reg = ioread32(sbc610_regs);
+       return (reg >> 8) & 0xff;
+}
+
+/* Return the board (software) revision */
+static unsigned int gef_sbc610_get_board_rev(void)
+{
+       unsigned int reg;
+
+       reg = ioread32(sbc610_regs);
+       return (reg >> 16) & 0xff;
 }
 
+/* Return the FPGA revision */
+static unsigned int gef_sbc610_get_fpga_rev(void)
+{
+       unsigned int reg;
+
+       reg = ioread32(sbc610_regs);
+       return (reg >> 24) & 0xf;
+}
 
 static void gef_sbc610_show_cpuinfo(struct seq_file *m)
 {
@@ -96,6 +131,10 @@ static void gef_sbc610_show_cpuinfo(struct seq_file *m)
 
        seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
 
+       seq_printf(m, "Revision\t: %u%c\n", gef_sbc610_get_pcb_rev(),
+               ('A' + gef_sbc610_get_board_rev() - 1));
+       seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc610_get_fpga_rev());
+
        seq_printf(m, "SVR\t\t: 0x%x\n", svid);
        seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 }

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