Hi,
I'm trying to enable the MEI on my graphics card, to allow for firmware
updates. The MEI is enumerated through an auxiliary bus, so it is
detected only when the main driver is loaded.
The MEI driver tries to register an interrupt. On PPC64 (LE), I get:
xe 0030:03:00.0: enabling device (0140 -> 0142)
xe 0030:03:00.0: [drm] unbounded parent pci bridge, device won't support
any PM support.
xe 0030:03:00.0: [drm] Found battlemage (device ID e20b) discrete
display version 14.01 stepping B0
...
pci 0030:02:01.0: Failed to create device link (0x124) with supplier
0.interrupt-controller for /pciex@620c3c0000000/pci@0/pci@0/pci@1
pci 0030:01:00.0: Failed to create device link (0x124) with supplier
0.interrupt-controller for /pciex@620c3c0000000/pci@0/pci@0
pci 0030:00:00.0: Failed to create device link (0x124) with supplier
0.interrupt-controller for /pciex@620c3c0000000/pci@0
mei_gsc xe.mei-gscfi.3146496: irq register failed -22
mei_gsc xe.mei-gscfi.3146496: probe failed: -22
mei_gsc xe.mei-gscfi.3146496: probe with driver mei_gsc failed with
error -22
My initial suspicion was that this is caused by
pcie_ports_disabled = true;
in arch/powerpc/platforms/powernv/pci.c:784 which stops the pcieport
driver from being registered, and attaching to all the PCIe bridge
ports, so there is neither power management nor something for the device
link to attach to.
Simply commenting out this line does not change anything though: lspci
shows the driver as registered and bound to the bridges, but it still
complains about a lack of power management, still fails to create device
links, and still fails to register the irq for the MEI.
So clearly there is something I've overlooked, and I'm a bit less
confident now that the failure to register the IRQ is related to the
"device link" functionality.
Since the weekend is coming up and I should have a bit of time to try
things then:
1. how is this supposed to work on PPC? Should there be an OPAL call for
power management of non-root PCIe bridges (i.e. "someone should write a
driver"), or should non-root bridges be managed by pcieport as normal?
2. how is this interrupt supposed to work on Xe? is that a separate
interrupt that needs to be requested and routed in addition to the MSI
we already have, or is the MSI shared?
3. are these problems actually related, or did I misinterpret anything?
Simon
