On Tue, Apr 22, 2025, at 04:49, Ben Collins wrote:
> On 64-bit QorIQ platforms like T4240, the CPU supports 40-bit addressing
> and memory configurations > 64GiB. The fsldma driver is limiting itself
> to only 64GiB in all Elo configurations.
>
> Setup fsldma driver to make use of the full 40-bit addressing space,
> specifically on the e5500 and e6500 CPUs.
I don't think making the mask depend on a compile-time option is
correct, e.g. when you build a combined 32-bit kernel for e500 and
e5500, you set a different mask compared to an e500-only kernel.
The question here is whether the mask is a limitation of the
IP block or the bus it's connected to, of if there is any
limitation at all:
- The driver just writes the DMA address as a 64-bit register,
so most likely the DMA device can in fact do wider addressing,
and any limitation is either in the bus or the available
memory
- SoCs that don't set a dma-ranges property in the parent bus
are normally still capped to 32 bit DMA. I don't see those
properties, so unless there is a special hack on those chips,
you get 32 bit DMA regardless of what DMA mask the driver
requests
- If there are chips that have more than 64GB of RAM installed
but have a limitation in the way the DMA engine is wired
up to 36 bits, that should be reflected in the dma-ranges
property, not the device driver.
- If the limitation is indeed specific to the version of the
IP block, this would normally need to be detected based on
the compatible string of the DMA engine itself, not a compile
time setting.
Arnd
