On Thu, 08 Aug 2024 09:11:00 +0200, Herve Codina wrote: > Add support for the time slot assigner (TSA) available in some > PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321. > > This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified > Communication Controllers) instead of SCCs (Serial Communication > Controllers). Also, compared against the CPM TSA, this QE TSA can handle > up to 4 TDMs instead of 2 and allows to configure the logic level of > sync signals. > > Signed-off-by: Herve Codina <herve.cod...@bootlin.com> > --- > .../bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml | 210 ++++++++++++++++++ > include/dt-bindings/soc/qe-fsl,tsa.h | 13 ++ > 2 files changed, 223 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml > create mode 100644 include/dt-bindings/soc/qe-fsl,tsa.h >
Reviewed-by: Rob Herring (Arm) <r...@kernel.org>
