On Fri, 05 May 2023 19:28:18 +0200, Pali Rohár wrote:
> Freescale PCIe controllers on their PCIe Root Ports do not have any
> mappable PCI BAR allocate from PCIe MEM.
>
> Information about 1MB window on BAR0 of PCIe Root Port was misleading
> because Freescale PCIe controllers have at BAR0 position different register
> PEXCSRBAR, and kernel correctly skipts BAR0 for these Freescale PCIe Root
> Ports.
>
> [...]
Applied to powerpc/next.
[1/1] powerpc: dts: turris1x.dts: Fix PCIe MEM size for pci2 node
https://git.kernel.org/powerpc/c/abaa02fc944f2f9f2c2e1925ddaceaf35c48528c
cheers
