mmiowb must ensure MMIO stores inside a spin lock critical section on one CPU will not be seen by the device after another CPU takes the same lock and performs MMIOs.
This just requires cache inhibited stores to be ordered with the store to unlock the spinlock, so wmb() can be used. Signed-off-by: Nicholas Piggin <npig...@gmail.com> --- arch/powerpc/include/asm/mmiowb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/mmiowb.h b/arch/powerpc/include/asm/mmiowb.h index 74a00127eb20..cd071fb97eba 100644 --- a/arch/powerpc/include/asm/mmiowb.h +++ b/arch/powerpc/include/asm/mmiowb.h @@ -9,7 +9,7 @@ #include <asm/paca.h> #define arch_mmiowb_state() (&local_paca->mmiowb_state) -#define mmiowb() mb() +#define mmiowb() wmb() #endif /* CONFIG_MMIOWB */ -- 2.40.1
