> This is all about inbound transfers, i.e. DMAs coming from the I/O bridge > into the CPU, both DMA read and DMA write.
OK -- at a minimum I think the documentation should make that clear. As it stands the description of what this does is pretty much impossible to parse and understand. > Strong ordering is only active when both the bridge and the IOMMU enable > it, but for correctly written drivers, this only results in a slowdown. So when would someone use this dma attribute? As a hack to fix drivers where the real fix is too complicated? - R. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
