Hi! On Mon, Nov 07, 2022 at 02:31:59PM +1100, Rohan McLure wrote: > Add Kconfig option for enabling clearing of registers on arrival in an > interrupt handler. This reduces the speculation influence of registers > on kernel internals.
Assuming you are talking about existing PowerPC CPUs from the last 30 years: There is no data speculation. At all. Ever. There is branch prediction, but that is not influenced by register contents, either (for any current CPUs at least). (Except when you get a flush because of a mispredict, but if this zeroing changes anything, we will have used wild (but user controlled) values in the old non-zeroing situation, and that is a much bigger problem itself already, also for security! This can be an unlikely kernel bug, or a very unlikely compiler bug.) All GPRs are renamed, always. If you zero all GPRs on interrupt entry (which is context synchronising, importantly), this will guarantee there can be no timing influence from the GPRs, because all of the physical registers depend on nothing that happened before. So that is good, at least it can give some peace of mind. Except that this makes 30 new registers in just a few cycles, which *itself* can cause stalls, if the renaming things are still busy. Context synchronising does not necessarily help there, the renaming machinery can do stuff *after* an insn completes. I don't see how this helps anything. If it does, "reduces speculation influence" is not a good description of what it does, afaics? Segher
