On Fri, 20 May 2022 22:36:49 +1000, Nicholas Piggin wrote:
> Processors with coherent icache require the sequence sync ; icbi ; isync
> to entire store->execute coherency. icbi (to any address) must be
> executed to ensure isync flushes the pipeline. See "POWER9 Processor
> User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi)" for
> details.
>
> __kernel_sync_dicache is missing icbi for the coherent icache path.
> Add it.
>
> [...]
Applied to powerpc/next.
[1/1] powerpc/vdso: Fix __kernel_sync_dicache sequence with coherent icache
https://git.kernel.org/powerpc/c/28f07fab26319dacc5675ae01dfc84d82122c59b
cheers
